Application of low-frequency clock signals to gate driver circuits

Chin Lung Lin; Mao Hsun Cheng

doi:10.1002/sdtp.11559

Application of low-frequency clock signals to gate driver circuits

Chin Lung Lin
, Mao Hsun Cheng

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Citations (Scopus)

Abstract

This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔV_TH).

Original language	English
Pages (from-to)	64-67
Number of pages	4
Journal	Digest of Technical Papers - SID International Symposium
Volume	48
Issue number	1
DOIs	https://doi.org/10.1002/sdtp.11559
Publication status	Published - 2017
Event	SID Symposium, Seminar, and Exhibition 2017, Display Week 2017 - Los Angeles, United States Duration: 2017 May 21 → 2017 May 26

All Science Journal Classification (ASJC) codes

General Engineering

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10.1002/sdtp.11559

Cite this

@article{f5ddee485178481d98502ad5f7cf66e5,

title = "Application of low-frequency clock signals to gate driver circuits",

abstract = "This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔVTH).",

author = "Lin, \{Chin Lung\} and Cheng, \{Mao Hsun\}",

note = "Funding Information: The authors would like to thank the Ministry of Science and Technology, Taiwan, for financially supporting this research under contract no. MOST 104-2221-E-006-189-MY3. Also, the authors acknowledge AU Optronics Corporation, Hsinchu, Taiwan, for its technical support. Publisher Copyright: {\textcopyright} (2017) by SID-the Society for Information Display. All rights reserved.; SID Symposium, Seminar, and Exhibition 2017, Display Week 2017 ; Conference date: 21-05-2017 Through 26-05-2017",

year = "2017",

doi = "10.1002/sdtp.11559",

language = "English",

volume = "48",

pages = "64--67",

journal = "Digest of Technical Papers - SID International Symposium",

issn = "0097-966X",

publisher = "John Wiley and Sons Inc.",

number = "1",

}

TY - JOUR

T1 - Application of low-frequency clock signals to gate driver circuits

AU - Lin, Chin Lung

AU - Cheng, Mao Hsun

N1 - Funding Information: The authors would like to thank the Ministry of Science and Technology, Taiwan, for financially supporting this research under contract no. MOST 104-2221-E-006-189-MY3. Also, the authors acknowledge AU Optronics Corporation, Hsinchu, Taiwan, for its technical support. Publisher Copyright: © (2017) by SID-the Society for Information Display. All rights reserved.

PY - 2017

Y1 - 2017

N2 - This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔVTH).

AB - This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔVTH).

UR - https://www.scopus.com/pages/publications/85044474568

UR - https://www.scopus.com/pages/publications/85044474568#tab=citedBy

U2 - 10.1002/sdtp.11559

DO - 10.1002/sdtp.11559

M3 - Conference article

AN - SCOPUS:85044474568

SN - 0097-966X

VL - 48

SP - 64

EP - 67

JO - Digest of Technical Papers - SID International Symposium

JF - Digest of Technical Papers - SID International Symposium

IS - 1

T2 - SID Symposium, Seminar, and Exhibition 2017, Display Week 2017

Y2 - 21 May 2017 through 26 May 2017

ER -

Application of low-frequency clock signals to gate driver circuits

Abstract

All Science Journal Classification (ASJC) codes

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