Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers

Hsiang Chih Hsiao, Chun Wei Chen, Jonas Wang, Ming Der Shieh, Pei Yin Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.

Original languageEnglish
Title of host publicationProceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728100739
DOIs
Publication statusPublished - 2019 Apr
Event22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 - Cluj-Napoca, Romania
Duration: 2019 Apr 242019 Apr 26

Publication series

NameProceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019

Conference

Conference22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
CountryRomania
CityCluj-Napoca
Period19-04-2419-04-26

Fingerprint

High Throughput
Classifiers
Classifier
Scheduling
Throughput
Graph Model
Data storage equipment
Hardware Accelerator
Circuit Complexity
Resource Constraints
Graph Coloring
Coloring
Coefficient
Post-processing
Feature Extraction
Particle accelerators
High Efficiency
Scheduling Problem
Feature extraction
Irregular

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Control and Optimization

Cite this

Hsiao, H. C., Chen, C. W., Wang, J., Shieh, M. D., & Chen, P. Y. (2019). Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 [8724671] (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DDECS.2019.8724671
Hsiao, Hsiang Chih ; Chen, Chun Wei ; Wang, Jonas ; Shieh, Ming Der ; Chen, Pei Yin. / Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019).
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Hsiao, HC, Chen, CW, Wang, J, Shieh, MD & Chen, PY 2019, Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. in Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019., 8724671, Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019, Institute of Electrical and Electronics Engineers Inc., 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019, Cluj-Napoca, Romania, 19-04-24. https://doi.org/10.1109/DDECS.2019.8724671

Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. / Hsiao, Hsiang Chih; Chen, Chun Wei; Wang, Jonas; Shieh, Ming Der; Chen, Pei Yin.

Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8724671 (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Hsiao HC, Chen CW, Wang J, Shieh MD, Chen PY. Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8724671. (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019). https://doi.org/10.1109/DDECS.2019.8724671