@inproceedings{9390d29e7e66456984c2936341f77ff1,
title = "Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers",
abstract = "Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.",
author = "Hsiao, {Hsiang Chih} and Chen, {Chun Wei} and Jonas Wang and Shieh, {Ming Der} and Chen, {Pei Yin}",
year = "2019",
month = apr,
doi = "10.1109/DDECS.2019.8724671",
language = "English",
series = "Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019",
address = "United States",
note = "22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 ; Conference date: 24-04-2019 Through 26-04-2019",
}