Abstract
Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728100739 |
| DOIs | |
| Publication status | Published - 2019 Apr |
| Event | 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 - Cluj-Napoca, Romania Duration: 2019 Apr 24 → 2019 Apr 26 |
Publication series
| Name | Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 |
|---|
Conference
| Conference | 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 |
|---|---|
| Country | Romania |
| City | Cluj-Napoca |
| Period | 19-04-24 → 19-04-26 |
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All Science Journal Classification (ASJC) codes
- Artificial Intelligence
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Control and Optimization
Cite this
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Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. / Hsiao, Hsiang Chih; Chen, Chun Wei; Wang, Jonas; Shieh, Ming Der; Chen, Pei Yin.
Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8724671 (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers
AU - Hsiao, Hsiang Chih
AU - Chen, Chun Wei
AU - Wang, Jonas
AU - Shieh, Ming Der
AU - Chen, Pei Yin
PY - 2019/4
Y1 - 2019/4
N2 - Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.
AB - Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.
UR - http://www.scopus.com/inward/record.url?scp=85067583515&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85067583515&partnerID=8YFLogxK
U2 - 10.1109/DDECS.2019.8724671
DO - 10.1109/DDECS.2019.8724671
M3 - Conference contribution
AN - SCOPUS:85067583515
T3 - Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
BT - Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
ER -