Architecture technique trade-offs using mean memory delay time

Chung Ho Chen, Arun K. Somani

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


Many architecture features are available for improving the performance of a cache-based system. These hardware techniques include cache memories, processor stalling characteristics, memory cycle time, the external data bus width of a processor, and pipelined memory system, etc. Each of these techniques affects the cost, design, and performance of a system. We present a powerful approach to assess the performance trade-offs of these architecture techniques based on the equivalence of mean memory delay time. For the same performance point, we demonstrate how each of these features can be traded off and report the ranking of the achievable performance of using them.

Original languageEnglish
Pages (from-to)1089-1100
Number of pages12
JournalIEEE Transactions on Computers
Issue number10
Publication statusPublished - 1996

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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