Area and test cost reduction for on-chip wireless test channels with system-level design techniques

Chun Kai Hsu, Li Ming Denq, Mao Yin Wang, Jing Jia Liou, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

With continuing trends to embed more on-chip test circuits, increasing complexity requires more efforts on design and validation. In this paper, we use a wireless test system as an example, to demonstrate the efficiency of system-level techniques in assisting circuit specification exploration, with the goal of area and test-cost reduction. In our experiments, 30% to 50% total costs are saved compared to an initial ad-hoc setup.

Original languageEnglish
Title of host publicationProceedings of the 17th Asian Test Symposium, ATS 2008
Pages245-250
Number of pages6
DOIs
Publication statusPublished - 2008 Dec 1
Event17th Asian Test Symposium, ATS 2008 - Sapporo, Japan
Duration: 2008 Nov 242008 Nov 27

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other17th Asian Test Symposium, ATS 2008
CountryJapan
CitySapporo
Period08-11-2408-11-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Hsu, C. K., Denq, L. M., Wang, M. Y., Liou, J. J., Huang, C. T., & Wu, C. W. (2008). Area and test cost reduction for on-chip wireless test channels with system-level design techniques. In Proceedings of the 17th Asian Test Symposium, ATS 2008 (pp. 245-250). [4711591] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2008.19