ASLCScan: A scan design technique for asynchronous sequential logic circuits

Chin Long Wey, Ming Der Shieh, P. David Fisher

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Asynchronous sequential logic circuits (ASLCs) are synthesized with either the Huffman model, referred to as HMASLCs, or with the signal transition graph (STG), referred to as STGASLCs. Based on a single stuck-at fault model, this paper describes fault effects for both HMASLCs and STGASLCs and addresses the similarities and differences between them. The fault effects include redundant faults and state oscillations. Input/output redundancy is a special feature of STGASLCs which relaxes the fundamental mode in HMASLCs. Results of this study show that the faults due to the input/output concurrency cannot be tested without a scan structure. This paper presents a scan design technique, ASLCScan. With this scan structure, the test generation problem is reduced to one of just testing the combinational logic.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
Editors Anon
PublisherPubl by IEEE
Pages159-162
Number of pages4
ISBN (Print)0818642300
Publication statusPublished - 1993 Dec 1
EventProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
Duration: 1993 Oct 31993 Oct 6

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

OtherProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityCambridge, MA, USA
Period93-10-0393-10-06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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