Asymmetrical triple-gate FET

Meng Hsueh Chiang, Jeng Nan Lin, Keunwoo Kim, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

Original languageEnglish
Title of host publication2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
PublisherSpringer-Verlag Wien
Pages389-392
Number of pages4
ISBN (Print)9783211728604
DOIs
Publication statusPublished - 2007
Event12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 - Vienna, Austria
Duration: 2007 Sep 252007 Sep 27

Publication series

Name2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

Other

Other12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
CountryAustria
CityVienna
Period07-09-2507-09-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Modelling and Simulation

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