Asymmetrical triple-gate FET

Meng Hsueh Chiang; Jeng Nan Lin; Keunwoo Kim; Ching Te Chuang

doi:10.1007/978-3-211-72861-1_94

Asymmetrical triple-gate FET

Meng Hsueh Chiang, Jeng Nan Lin, Keunwoo Kim, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n⁺/p⁺) polysilicon gates. CMOS-compatible V_T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

Original language	English
Title of host publication	2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
Publisher	Springer-Verlag Wien
Pages	389-392
Number of pages	4
ISBN (Print)	9783211728604
DOIs	https://doi.org/10.1007/978-3-211-72861-1_94
Publication status	Published - 2007
Event	12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 - Vienna, Austria Duration: 2007 Sep 25 → 2007 Sep 27

Publication series

Name	2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

Other

Other	12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
Country	Austria
City	Vienna
Period	07-09-25 → 07-09-27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Modelling and Simulation

Access to Document

10.1007/978-3-211-72861-1_94

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Cite this

@inproceedings{d2da49a85806405cb91f7bb67b3412cd,

title = "Asymmetrical triple-gate FET",

abstract = "A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.",

author = "Chiang, {Meng Hsueh} and Lin, {Jeng Nan} and Keunwoo Kim and Chuang, {Ching Te}",

note = "Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 ; Conference date: 25-09-2007 Through 27-09-2007",

year = "2007",

doi = "10.1007/978-3-211-72861-1_94",

language = "English",

isbn = "9783211728604",

series = "2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007",

publisher = "Springer-Verlag Wien",

pages = "389--392",

booktitle = "2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007",

address = "Austria",

}

Chiang, MH, Lin, JN, Kim, K & Chuang, CT 2007, Asymmetrical triple-gate FET. in 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007. 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Springer-Verlag Wien, pp. 389-392, 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria, 07-09-25. https://doi.org/10.1007/978-3-211-72861-1_94

Asymmetrical triple-gate FET. / Chiang, Meng Hsueh; Lin, Jeng Nan; Kim, Keunwoo; Chuang, Ching Te.

2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007. Springer-Verlag Wien, 2007. p. 389-392 (2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Asymmetrical triple-gate FET

AU - Chiang, Meng Hsueh

AU - Lin, Jeng Nan

AU - Kim, Keunwoo

AU - Chuang, Ching Te

PY - 2007

Y1 - 2007

N2 - A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

AB - A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

UR - http://www.scopus.com/inward/record.url?scp=84901357739&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84901357739&partnerID=8YFLogxK

U2 - 10.1007/978-3-211-72861-1_94

DO - 10.1007/978-3-211-72861-1_94

M3 - Conference contribution

AN - SCOPUS:84901357739

SN - 9783211728604

T3 - 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

SP - 389

EP - 392

BT - 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

PB - Springer-Verlag Wien

T2 - 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

Y2 - 25 September 2007 through 27 September 2007

ER -