Asynchronous design methodology for an efficient implementation of low power ALU

P. Manikandan; B. D. Liu; L. Y. Chiou; G. Sundar; C. R. Mandal

doi:10.1109/APCCAS.2006.342057

Asynchronous design methodology for an efficient implementation of low power ALU

P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, C. R. Mandal

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	590-593
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342057
Publication status	Published - 2006
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: 2006 Dec 4 → 2006 Dec 6

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	06-12-04 → 06-12-06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2006.342057

Cite this

Manikandan, P., Liu, B. D., Chiou, L. Y., Sundar, G., & Mandal, C. R. (2006). Asynchronous design methodology for an efficient implementation of low power ALU. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 590-593). Article 4145462 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342057

@inproceedings{40d9ead9b6ab4e0aa0e94c3b73a75285,

title = "Asynchronous design methodology for an efficient implementation of low power ALU",

abstract = "We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay.",

author = "P. Manikandan and Liu, {B. D.} and Chiou, {L. Y.} and G. Sundar and Mandal, {C. R.}",

year = "2006",

doi = "10.1109/APCCAS.2006.342057",

language = "English",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "590--593",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

}

Manikandan, P, Liu, BD, Chiou, LY, Sundar, G & Mandal, CR 2006, Asynchronous design methodology for an efficient implementation of low power ALU. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145462, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 590-593, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06-12-04. https://doi.org/10.1109/APCCAS.2006.342057

Asynchronous design methodology for an efficient implementation of low power ALU. / Manikandan, P.; Liu, B. D.; Chiou, L. Y. et al.
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 590-593 4145462 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Asynchronous design methodology for an efficient implementation of low power ALU

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AU - Sundar, G.

AU - Mandal, C. R.

PY - 2006

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N2 - We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay.

AB - We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay.

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DO - 10.1109/APCCAS.2006.342057

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T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

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BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

Asynchronous design methodology for an efficient implementation of low power ALU

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