Asynchronous design methodology for an efficient implementation of low power ALU

P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, C. R. Mandal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages590-593
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 2006 Dec 42006 Dec 6

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
CountrySingapore
Period06-12-0406-12-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Asynchronous design methodology for an efficient implementation of low power ALU'. Together they form a unique fingerprint.

Cite this