Automated synthesis of asynchronous pipelines

Yau Hwang Kuo, Shaw Pyng Lo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper proposes a system for the automatic synthesis of asynchronous pipelines. A high-level hardware description language (HDL), called Masil-II, is developed to describe the circuit behavior at algorithmic level. Modified Petri-Net is used as intermediate description. From the intermediate description, several techniques such as clique partitioning, simulated evolution and heuristics are applied to realize the data path synthesis task. Experimental results have confirmed their efficiency.

Original languageEnglish
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages685-688
Number of pages4
ISBN (Electronic)0780305930
DOIs
Publication statusPublished - 1992 Jan 1
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: 1992 May 101992 May 13

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period92-05-1092-05-13

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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