Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC

Wei Hao Hsiao, Yi Ting He, Mark Po Hung Lin, Rong Guey Chang, Shuenn-Yuh Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.

Original languageEnglish
Title of host publication2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
Pages173-176
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 11
Event2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 - Seville, Spain
Duration: 2012 Sep 192012 Sep 21

Publication series

Name2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012

Other

Other2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
CountrySpain
CitySeville
Period12-09-1912-09-21

Fingerprint

Capacitor
Centroid
Layout
Capacitors
Charge
Scaling
Binary
Networks (circuits)
Digital to analog conversion
Capacitance
Analog-to-digital Converter
Placement
Routing
Minimise
Optimization
Experimental Results

All Science Journal Classification (ASJC) codes

  • Modelling and Simulation

Cite this

Hsiao, W. H., He, Y. T., Lin, M. P. H., Chang, R. G., & Lee, S-Y. (2012). Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC. In 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 (pp. 173-176). [6339445] (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012). https://doi.org/10.1109/SMACD.2012.6339445
Hsiao, Wei Hao ; He, Yi Ting ; Lin, Mark Po Hung ; Chang, Rong Guey ; Lee, Shuenn-Yuh. / Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012. 2012. pp. 173-176 (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012).
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title = "Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC",
abstract = "As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.",
author = "Hsiao, {Wei Hao} and He, {Yi Ting} and Lin, {Mark Po Hung} and Chang, {Rong Guey} and Shuenn-Yuh Lee",
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series = "2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012",
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booktitle = "2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012",

}

Hsiao, WH, He, YT, Lin, MPH, Chang, RG & Lee, S-Y 2012, Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC. in 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012., 6339445, 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012, pp. 173-176, 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012, Seville, Spain, 12-09-19. https://doi.org/10.1109/SMACD.2012.6339445

Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC. / Hsiao, Wei Hao; He, Yi Ting; Lin, Mark Po Hung; Chang, Rong Guey; Lee, Shuenn-Yuh.

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012. 2012. p. 173-176 6339445 (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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T1 - Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC

AU - Hsiao, Wei Hao

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AB - As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.

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Hsiao WH, He YT, Lin MPH, Chang RG, Lee S-Y. Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC. In 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012. 2012. p. 173-176. 6339445. (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012). https://doi.org/10.1109/SMACD.2012.6339445