Memory testing is becoming the dominant factor in testing a system-on-chip (SOC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SOC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SOC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Media Technology