Abstract
Memory testing is becoming the dominant factor in testing a system-on-chip (SOC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SOC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SOC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.
Original language | English |
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Pages (from-to) | 91-96 |
Number of pages | 6 |
Journal | Proceedings of the Asian Test Symposium |
Publication status | Published - 2001 Dec 1 |
Event | Proceedings of the 10th Asian Test Symposium - Kyoto, Japan Duration: 2001 Nov 19 → 2001 Nov 21 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Media Technology