Autonomous Testing for 3D-ICs with IEEE Std. 1687

Jin Cun Ye; Michael A. Kochte; Kuen Jong Lee; Hans Joachim Wunderlich

doi:10.1109/ATS.2016.56

Autonomous Testing for 3D-ICs with IEEE Std. 1687

Jin Cun Ye, Michael A. Kochte, Kuen Jong Lee, Hans Joachim Wunderlich

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.

Original language	English
Title of host publication	Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016
Publisher	IEEE Computer Society
Pages	215-220
Number of pages	6
ISBN (Electronic)	9781509038084
DOIs	https://doi.org/10.1109/ATS.2016.56
Publication status	Published - 2016 Dec 22
Event	25th IEEE Asian Test Symposium, ATS 2016 - Hiroshima, Japan Duration: 2016 Nov 21 → 2016 Nov 24

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Other

Other	25th IEEE Asian Test Symposium, ATS 2016
Country/Territory	Japan
City	Hiroshima
Period	16-11-21 → 16-11-24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ATS.2016.56

Cite this

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title = "Autonomous Testing for 3D-ICs with IEEE Std. 1687",

abstract = "IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.",

author = "Ye, {Jin Cun} and Kochte, {Michael A.} and Lee, {Kuen Jong} and Wunderlich, {Hans Joachim}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 25th IEEE Asian Test Symposium, ATS 2016 ; Conference date: 21-11-2016 Through 24-11-2016",

year = "2016",

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doi = "10.1109/ATS.2016.56",

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AU - Ye, Jin Cun

AU - Kochte, Michael A.

AU - Lee, Kuen Jong

AU - Wunderlich, Hans Joachim

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Y1 - 2016/12/22

N2 - IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.

AB - IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.

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M3 - Conference contribution

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BT - Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016

PB - IEEE Computer Society

T2 - 25th IEEE Asian Test Symposium, ATS 2016

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ER -

Autonomous Testing for 3D-ICs with IEEE Std. 1687

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