Abstract
IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016 |
| Publisher | IEEE Computer Society |
| Pages | 215-220 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781509038084 |
| DOIs | |
| Publication status | Published - 2016 Dec 22 |
| Event | 25th IEEE Asian Test Symposium, ATS 2016 - Hiroshima, Japan Duration: 2016 Nov 21 → 2016 Nov 24 |
Publication series
| Name | Proceedings of the Asian Test Symposium |
|---|---|
| ISSN (Print) | 1081-7735 |
Other
| Other | 25th IEEE Asian Test Symposium, ATS 2016 |
|---|---|
| Country | Japan |
| City | Hiroshima |
| Period | 16-11-21 → 16-11-24 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Autonomous Testing for 3D-ICs with IEEE Std. 1687. / Ye, Jin Cun; Kochte, Michael A.; Lee, Kuen Jong; Wunderlich, Hans Joachim.
Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, 2016. p. 215-220 7796115 (Proceedings of the Asian Test Symposium).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Autonomous Testing for 3D-ICs with IEEE Std. 1687
AU - Ye, Jin Cun
AU - Kochte, Michael A.
AU - Lee, Kuen Jong
AU - Wunderlich, Hans Joachim
PY - 2016/12/22
Y1 - 2016/12/22
N2 - IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.
AB - IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.
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UR - http://www.scopus.com/inward/citedby.url?scp=85010210739&partnerID=8YFLogxK
U2 - 10.1109/ATS.2016.56
DO - 10.1109/ATS.2016.56
M3 - Conference contribution
AN - SCOPUS:85010210739
T3 - Proceedings of the Asian Test Symposium
SP - 215
EP - 220
BT - Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016
PB - IEEE Computer Society
ER -