The lifetime degradation of new multi-level cell (MLC) flash devices is becoming more and more serious due to the fast-increasing bit error rate variance among flash pages, where a flash chip consists of multiple blocks and each block consists of a fixed number of pages. Existing works usually discard bad pages in the unit of a block, but result in shortened the device lifetime due to the insufficient storage capacity. This issue is exacerbated when new MLC flash devices are adopted. In contrast to existing works, we propose a bad page relaxation scheme to ultimately extend the device lifetime by discarding bad pages in the unit of a page. The proposed scheme takes advantage of the high flexibility of page-level mapping strategies in reading/writing pages to avoid management overheads. The experiments were conducted based on representative realistic workloads to evaluate the efficacy of the proposed scheme, and the results are very encouraging.