Bayesian neural network chip design for speech recognition system

Jhing Fa Wang, An Nan Suen, Jia Ru Lee, Chung-Hsien Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.

Original languageEnglish
Title of host publicationIEEE International Conference on Neural Networks - Conference Proceedings
PublisherIEEE
Pages2027-2030
Number of pages4
Volume4
Publication statusPublished - 1995
EventProceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6) - Perth, Aust
Duration: 1995 Nov 271995 Dec 1

Other

OtherProceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6)
CityPerth, Aust
Period95-11-2795-12-01

Fingerprint

Speech recognition
Neural networks
Hidden Markov models
Dynamic programming
Costs
Transistors
Metals

All Science Journal Classification (ASJC) codes

  • Software

Cite this

Wang, J. F., Suen, A. N., Lee, J. R., & Wu, C-H. (1995). Bayesian neural network chip design for speech recognition system. In IEEE International Conference on Neural Networks - Conference Proceedings (Vol. 4, pp. 2027-2030). IEEE.
Wang, Jhing Fa ; Suen, An Nan ; Lee, Jia Ru ; Wu, Chung-Hsien. / Bayesian neural network chip design for speech recognition system. IEEE International Conference on Neural Networks - Conference Proceedings. Vol. 4 IEEE, 1995. pp. 2027-2030
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abstract = "The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.",
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Wang, JF, Suen, AN, Lee, JR & Wu, C-H 1995, Bayesian neural network chip design for speech recognition system. in IEEE International Conference on Neural Networks - Conference Proceedings. vol. 4, IEEE, pp. 2027-2030, Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6), Perth, Aust, 95-11-27.

Bayesian neural network chip design for speech recognition system. / Wang, Jhing Fa; Suen, An Nan; Lee, Jia Ru; Wu, Chung-Hsien.

IEEE International Conference on Neural Networks - Conference Proceedings. Vol. 4 IEEE, 1995. p. 2027-2030.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.

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Wang JF, Suen AN, Lee JR, Wu C-H. Bayesian neural network chip design for speech recognition system. In IEEE International Conference on Neural Networks - Conference Proceedings. Vol. 4. IEEE. 1995. p. 2027-2030