Bayesian neural network chip design for speech recognition system

Jhing Fa Wang; An Nan Suen; Jia Ru Lee; Chung Hsien Wu

Bayesian neural network chip design for speech recognition system

Jhing Fa Wang
, An Nan Suen
, Jia Ru Lee
, Chung Hsien Wu

Department of Computer Science and Information Engineering

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm² area and has been tested to be fully functional at IMS XL-60 tester.

Original language	English
Pages	2027-2030
Number of pages	4
Publication status	Published - 1995 Dec 1
Event	Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6) - Perth, Aust Duration: 1995 Nov 27 → 1995 Dec 1

Other

Other	Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6)
City	Perth, Aust
Period	95-11-27 → 95-12-01

All Science Journal Classification (ASJC) codes

Software

Cite this

@conference{5168b824b10a40f781577e824f0ad1e4,

title = "Bayesian neural network chip design for speech recognition system",

abstract = "The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.",

author = "Wang, \{Jhing Fa\} and Suen, \{An Nan\} and Lee, \{Jia Ru\} and Wu, \{Chung Hsien\}",

year = "1995",

month = dec,

day = "1",

language = "English",

pages = "2027--2030",

note = "Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6) ; Conference date: 27-11-1995 Through 01-12-1995",

}

TY - CONF

T1 - Bayesian neural network chip design for speech recognition system

AU - Wang, Jhing Fa

AU - Suen, An Nan

AU - Lee, Jia Ru

AU - Wu, Chung Hsien

PY - 1995/12/1

Y1 - 1995/12/1

N2 - The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.

AB - The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.

UR - https://www.scopus.com/pages/publications/0029514615

UR - https://www.scopus.com/pages/publications/0029514615#tab=citedBy

M3 - Paper

AN - SCOPUS:0029514615

SP - 2027

EP - 2030

T2 - Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6)

Y2 - 27 November 1995 through 1 December 1995

ER -

Bayesian neural network chip design for speech recognition system

Abstract

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