Behavior model for comparator-based switched-capacitor SDM with relaxed DEM timing

I. Jen Chao, Chung Lun Hsu, Bin Da Liu, Chun Yueh Huang, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a behavior model for comparator-based switched-capacitor (CBSC) circuits by using SIMULINK platform. In this model, the maximum available time is compared with the charge transfer time required in the CBSC circuit to identify whether the currents chosen are suitable or not. The model is efficient to determine the values of the coarse charging current and the fine charging current required for CBSC circuits in a sigma-delta modulator (SDM). To verify the behavior model, a 3rd order SDM which still retains a half of the clock cycle for quantization and dynamic element matching (DEM) is proposed and simulated. The simulation result shows that the value of SNDR achieves 82.23 dB when the sampling rate is 100 MS/s (OSR=16).

Original languageEnglish
Title of host publication1st International Conference on Green Circuits and Systems, ICGCS 2010
Pages495-498
Number of pages4
DOIs
Publication statusPublished - 2010 Sep 20
Event1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai, China
Duration: 2010 Jun 212010 Jun 23

Publication series

Name1st International Conference on Green Circuits and Systems, ICGCS 2010

Other

Other1st International Conference on Green Circuits and Systems, ICGCS 2010
CountryChina
CityShanghai
Period10-06-2110-06-23

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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