A new built-in self-test (BIST)-based diagnosis scheme for field programmable gate array (FPGA) interconnect delay faults is proposed. Faulty paths can be located after configuring the output response analyser of the BIST circuit as a scan chain. By analysing these faulty paths, segment fault candidates can be obtained. The proposed diagnosis scheme can find effective test paths to locate faulty segment candidates. Experimental results for an island-style FPGA show high diagnosis resolution in locating the faulty paths, under single- and double-fault models caused by single and double defects, respectively.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering