TY - GEN
T1 - Bit level concurrency in real-time geometric feature extractions.
AU - Liu, Wentai
AU - Yeh, Tong Fei
AU - Batchelor, William E.
AU - Cavin, Ralph
PY - 1988
Y1 - 1988
N2 - An efficient mapping frame a tree structure into a pipelined array of 2log N stages is presented for processing an N × N image. In the proposed mapping structure, the identification of the information growing property inherent in feature-extraction algorithms allows bit-level concurrency to be exploited in the architectural design. Accordingly, the design of each staged pipelined processor is simplified.
AB - An efficient mapping frame a tree structure into a pipelined array of 2log N stages is presented for processing an N × N image. In the proposed mapping structure, the identification of the information growing property inherent in feature-extraction algorithms allows bit-level concurrency to be exploited in the architectural design. Accordingly, the design of each staged pipelined processor is simplified.
UR - https://www.scopus.com/pages/publications/0024136287
UR - https://www.scopus.com/pages/publications/0024136287#tab=citedBy
M3 - Conference contribution
AN - SCOPUS:0024136287
SN - 0818608625
T3 - Proc CVPR 88 Comput Soc Conf on Comput Vision and Pattern Recognit
SP - 957
EP - 962
BT - Proc CVPR 88 Comput Soc Conf on Comput Vision and Pattern Recognit
PB - Publ by IEEE
ER -