Bit-level systolic arrays for finite-field multiplications

Cheng Wen Wu, Ming Kwang Chang

Research output: Contribution to journalArticlepeer-review

15 Citations (Scopus)


Galois-field multiplication algorithms and their systolic realizations are proposed. Parallel and serial architectures as well as their VLSI implementations are presented. They are based on the standard-basis representation of the Galois-field elements. Our algorithms allow the two operands to enter the systolic arrays in the same order. Only one control signal for the serial systolic array is required as compared to two in the previous design. Our multipliers are more regular and modular, requiring simple control signal, and compact in terms of silicon area; they are well suited to VLSI implementation. Expansion to higher order Galois fields are easier to realize than other multipliers. High throughput rates are achieved due to their systolic array architectures.

Original languageEnglish
Pages (from-to)85-92
Number of pages8
JournalJournal of VLSI Signal Processing
Issue number1
Publication statusPublished - 1995 Jun 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing
  • Information Systems
  • Theoretical Computer Science
  • Hardware and Architecture


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