Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads

Tz-Cheng Chiu, Jyun Ji Lin, Vikas Gupta, Darvin Edwards, Mudasir Ahmad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The ever increasing power density in high performance microelectronic devices for large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. In this study, the effect of heatsinking compressive load on the solder joint reliability is investigated by using both experimental and numerical approaches. A phenomenological life prediction model for both Sn36Pn2Ag and Sn3.8Ag0.7Cu solder joints subjected to constant compressive load is also proposed.

Original languageEnglish
Title of host publication2010 12th Electronics Packaging Technology Conference, EPTC 2010
Pages646-651
Number of pages6
DOIs
Publication statusPublished - 2010
Event12th Electronics Packaging Technology Conference, EPTC 2010 - Singapore, Singapore
Duration: 2010 Dec 82010 Dec 10

Other

Other12th Electronics Packaging Technology Conference, EPTC 2010
CountrySingapore
CitySingapore
Period10-12-0810-12-10

Fingerprint

Ball grid arrays
Soldering alloys
Microelectronics
Telecommunication
Creep
Industry

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chiu, T-C., Lin, J. J., Gupta, V., Edwards, D., & Ahmad, M. (2010). Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. In 2010 12th Electronics Packaging Technology Conference, EPTC 2010 (pp. 646-651). [5702718] https://doi.org/10.1109/EPTC.2010.5702718
Chiu, Tz-Cheng ; Lin, Jyun Ji ; Gupta, Vikas ; Edwards, Darvin ; Ahmad, Mudasir. / Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. 2010 12th Electronics Packaging Technology Conference, EPTC 2010. 2010. pp. 646-651
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Chiu, T-C, Lin, JJ, Gupta, V, Edwards, D & Ahmad, M 2010, Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. in 2010 12th Electronics Packaging Technology Conference, EPTC 2010., 5702718, pp. 646-651, 12th Electronics Packaging Technology Conference, EPTC 2010, Singapore, Singapore, 10-12-08. https://doi.org/10.1109/EPTC.2010.5702718

Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. / Chiu, Tz-Cheng; Lin, Jyun Ji; Gupta, Vikas; Edwards, Darvin; Ahmad, Mudasir.

2010 12th Electronics Packaging Technology Conference, EPTC 2010. 2010. p. 646-651 5702718.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - The ever increasing power density in high performance microelectronic devices for large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. In this study, the effect of heatsinking compressive load on the solder joint reliability is investigated by using both experimental and numerical approaches. A phenomenological life prediction model for both Sn36Pn2Ag and Sn3.8Ag0.7Cu solder joints subjected to constant compressive load is also proposed.

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Chiu T-C, Lin JJ, Gupta V, Edwards D, Ahmad M. Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. In 2010 12th Electronics Packaging Technology Conference, EPTC 2010. 2010. p. 646-651. 5702718 https://doi.org/10.1109/EPTC.2010.5702718