Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads

Tz Cheng Chiu; Jyun Ji Lin; Vikas Gupta; Darvin Edwards; Mudasir Ahmad

doi:10.1109/EPTC.2010.5702718

Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads

Tz Cheng Chiu
, Jyun Ji Lin
, Vikas Gupta
, Darvin Edwards
, Mudasir Ahmad

Department of Mechanical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

The ever increasing power density in high performance microelectronic devices for large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. In this study, the effect of heatsinking compressive load on the solder joint reliability is investigated by using both experimental and numerical approaches. A phenomenological life prediction model for both Sn36Pn2Ag and Sn3.8Ag0.7Cu solder joints subjected to constant compressive load is also proposed.

Original language	English
Title of host publication	2010 12th Electronics Packaging Technology Conference, EPTC 2010
Pages	646-651
Number of pages	6
DOIs	https://doi.org/10.1109/EPTC.2010.5702718
Publication status	Published - 2010
Event	12th Electronics Packaging Technology Conference, EPTC 2010 - Singapore, Singapore Duration: 2010 Dec 8 → 2010 Dec 10

Publication series

Name	2010 12th Electronics Packaging Technology Conference, EPTC 2010

Other

Other	12th Electronics Packaging Technology Conference, EPTC 2010
Country/Territory	Singapore
City	Singapore
Period	10-12-08 → 10-12-10

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/EPTC.2010.5702718

Cite this

Chiu, T. C., Lin, J. J., Gupta, V., Edwards, D., & Ahmad, M. (2010). Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. In 2010 12th Electronics Packaging Technology Conference, EPTC 2010 (pp. 646-651). Article 5702718 (2010 12th Electronics Packaging Technology Conference, EPTC 2010). https://doi.org/10.1109/EPTC.2010.5702718

@inproceedings{96be73b57fc44ab286b739e75233ef59,

title = "Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads",

abstract = "The ever increasing power density in high performance microelectronic devices for large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. In this study, the effect of heatsinking compressive load on the solder joint reliability is investigated by using both experimental and numerical approaches. A phenomenological life prediction model for both Sn36Pn2Ag and Sn3.8Ag0.7Cu solder joints subjected to constant compressive load is also proposed.",

author = "Chiu, \{Tz Cheng\} and Lin, \{Jyun Ji\} and Vikas Gupta and Darvin Edwards and Mudasir Ahmad",

year = "2010",

doi = "10.1109/EPTC.2010.5702718",

language = "English",

isbn = "9781424485604",

series = "2010 12th Electronics Packaging Technology Conference, EPTC 2010",

pages = "646--651",

booktitle = "2010 12th Electronics Packaging Technology Conference, EPTC 2010",

note = "12th Electronics Packaging Technology Conference, EPTC 2010 ; Conference date: 08-12-2010 Through 10-12-2010",

}

Chiu, TC, Lin, JJ, Gupta, V, Edwards, D & Ahmad, M 2010, Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. in 2010 12th Electronics Packaging Technology Conference, EPTC 2010., 5702718, 2010 12th Electronics Packaging Technology Conference, EPTC 2010, pp. 646-651, 12th Electronics Packaging Technology Conference, EPTC 2010, Singapore, Singapore, 10-12-08. https://doi.org/10.1109/EPTC.2010.5702718

Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads. / Chiu, Tz Cheng; Lin, Jyun Ji; Gupta, Vikas et al.
2010 12th Electronics Packaging Technology Conference, EPTC 2010. 2010. p. 646-651 5702718 (2010 12th Electronics Packaging Technology Conference, EPTC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads

AU - Chiu, Tz Cheng

AU - Lin, Jyun Ji

AU - Gupta, Vikas

AU - Edwards, Darvin

AU - Ahmad, Mudasir

PY - 2010

Y1 - 2010

N2 - The ever increasing power density in high performance microelectronic devices for large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. In this study, the effect of heatsinking compressive load on the solder joint reliability is investigated by using both experimental and numerical approaches. A phenomenological life prediction model for both Sn36Pn2Ag and Sn3.8Ag0.7Cu solder joints subjected to constant compressive load is also proposed.

AB - The ever increasing power density in high performance microelectronic devices for large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. In this study, the effect of heatsinking compressive load on the solder joint reliability is investigated by using both experimental and numerical approaches. A phenomenological life prediction model for both Sn36Pn2Ag and Sn3.8Ag0.7Cu solder joints subjected to constant compressive load is also proposed.

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U2 - 10.1109/EPTC.2010.5702718

DO - 10.1109/EPTC.2010.5702718

M3 - Conference contribution

AN - SCOPUS:79951931844

SN - 9781424485604

T3 - 2010 12th Electronics Packaging Technology Conference, EPTC 2010

SP - 646

EP - 651

BT - 2010 12th Electronics Packaging Technology Conference, EPTC 2010

T2 - 12th Electronics Packaging Technology Conference, EPTC 2010

Y2 - 8 December 2010 through 10 December 2010

ER -

Board level solder joint reliability model for flip-chip ball grid array packages under compressive loads

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