Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM

Jheng Yi Chen, Ming Yu Chang, Shi Hao Chen, Jia Wei Lee, Meng-Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

Original languageEnglish
Title of host publication2018 19th International Symposium on Quality Electronic Design, ISQED 2018
PublisherIEEE Computer Society
Pages151-155
Number of pages5
ISBN (Electronic)9781538612149
DOIs
Publication statusPublished - 2018 May 9
Event19th International Symposium on Quality Electronic Design, ISQED 2018 - Santa Clara, United States
Duration: 2018 Mar 132018 Mar 14

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2018-March
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other19th International Symposium on Quality Electronic Design, ISQED 2018
CountryUnited States
CitySanta Clara
Period18-03-1318-03-14

Fingerprint

Static random access storage
Electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Chen, J. Y., Chang, M. Y., Chen, S. H., Lee, J. W., & Chiang, M-H. (2018). Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. In 2018 19th International Symposium on Quality Electronic Design, ISQED 2018 (pp. 151-155). (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2018-March). IEEE Computer Society. https://doi.org/10.1109/ISQED.2018.8357280
Chen, Jheng Yi ; Chang, Ming Yu ; Chen, Shi Hao ; Lee, Jia Wei ; Chiang, Meng-Hsueh. / Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, 2018. pp. 151-155 (Proceedings - International Symposium on Quality Electronic Design, ISQED).
@inproceedings{c35b2a821dae4c5e981979b95fffeeed,
title = "Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM",
abstract = "This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.",
author = "Chen, {Jheng Yi} and Chang, {Ming Yu} and Chen, {Shi Hao} and Lee, {Jia Wei} and Meng-Hsueh Chiang",
year = "2018",
month = "5",
day = "9",
doi = "10.1109/ISQED.2018.8357280",
language = "English",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "151--155",
booktitle = "2018 19th International Symposium on Quality Electronic Design, ISQED 2018",
address = "United States",

}

Chen, JY, Chang, MY, Chen, SH, Lee, JW & Chiang, M-H 2018, Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. in 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2018-March, IEEE Computer Society, pp. 151-155, 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, United States, 18-03-13. https://doi.org/10.1109/ISQED.2018.8357280

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. / Chen, Jheng Yi; Chang, Ming Yu; Chen, Shi Hao; Lee, Jia Wei; Chiang, Meng-Hsueh.

2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, 2018. p. 151-155 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM

AU - Chen, Jheng Yi

AU - Chang, Ming Yu

AU - Chen, Shi Hao

AU - Lee, Jia Wei

AU - Chiang, Meng-Hsueh

PY - 2018/5/9

Y1 - 2018/5/9

N2 - This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

AB - This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

UR - http://www.scopus.com/inward/record.url?scp=85047958065&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85047958065&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2018.8357280

DO - 10.1109/ISQED.2018.8357280

M3 - Conference contribution

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 151

EP - 155

BT - 2018 19th International Symposium on Quality Electronic Design, ISQED 2018

PB - IEEE Computer Society

ER -

Chen JY, Chang MY, Chen SH, Lee JW, Chiang M-H. Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. In 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society. 2018. p. 151-155. (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2018.8357280