Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM

Jheng Yi Chen; Ming Yu Chang; Shi Hao Chen; Jia Wei Lee; Meng Hsueh Chiang

doi:10.1109/ISQED.2018.8357280

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM

Jheng Yi Chen, Ming Yu Chang, Shi Hao Chen, Jia Wei Lee, Meng Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work proposes a body-biasing technique to optimize V_min of the 6T-SRAM based on 5nm-node multi-V_t FD-SOI devices. Accounting for the process variation, the operating voltage, V_min, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest V_min is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

Original language	English
Title of host publication	2018 19th International Symposium on Quality Electronic Design, ISQED 2018
Publisher	IEEE Computer Society
Pages	151-155
Number of pages	5
ISBN (Electronic)	9781538612149
DOIs	https://doi.org/10.1109/ISQED.2018.8357280
Publication status	Published - 2018 May 9
Event	19th International Symposium on Quality Electronic Design, ISQED 2018 - Santa Clara, United States Duration: 2018 Mar 13 → 2018 Mar 14

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2018-March
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	19th International Symposium on Quality Electronic Design, ISQED 2018
Country/Territory	United States
City	Santa Clara
Period	18-03-13 → 18-03-14

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISQED.2018.8357280

Cite this

Chen, J. Y., Chang, M. Y., Chen, S. H., Lee, J. W., & Chiang, M. H. (2018). Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. In 2018 19th International Symposium on Quality Electronic Design, ISQED 2018 (pp. 151-155). (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2018-March). IEEE Computer Society. https://doi.org/10.1109/ISQED.2018.8357280

@inproceedings{c35b2a821dae4c5e981979b95fffeeed,

title = "Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM",

abstract = "This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.",

author = "Chen, {Jheng Yi} and Chang, {Ming Yu} and Chen, {Shi Hao} and Lee, {Jia Wei} and Chiang, {Meng Hsueh}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 19th International Symposium on Quality Electronic Design, ISQED 2018 ; Conference date: 13-03-2018 Through 14-03-2018",

year = "2018",

month = may,

day = "9",

doi = "10.1109/ISQED.2018.8357280",

language = "English",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

publisher = "IEEE Computer Society",

pages = "151--155",

booktitle = "2018 19th International Symposium on Quality Electronic Design, ISQED 2018",

address = "United States",

}

Chen, JY, Chang, MY, Chen, SH, Lee, JW & Chiang, MH 2018, Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. in 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2018-March, IEEE Computer Society, pp. 151-155, 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, United States, 18-03-13. https://doi.org/10.1109/ISQED.2018.8357280

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. / Chen, Jheng Yi; Chang, Ming Yu; Chen, Shi Hao et al.
2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, 2018. p. 151-155 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Chiang, Meng Hsueh

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N2 - This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

AB - This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

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Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM

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