Buffer size minimization method considering mix-clock domains and discontinuous data access

Lih-Yih Chiou; Liang Ying Lu; Bo Chi Lin; Alan P. Su

doi:10.1109/APCCAS.2012.6419051

Buffer size minimization method considering mix-clock domains and discontinuous data access

Lih-Yih Chiou, Liang Ying Lu, Bo Chi Lin, Alan P. Su

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.

Original language	English
Title of host publication	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Pages	380-383
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2012.6419051
Publication status	Published - 2012 Dec 1
Event	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan Duration: 2012 Dec 2 → 2012 Dec 5

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Country/Territory	Taiwan
City	Kaohsiung
Period	12-12-02 → 12-12-05

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2012.6419051

Cite this

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title = "Buffer size minimization method considering mix-clock domains and discontinuous data access",

abstract = "We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.",

author = "Lih-Yih Chiou and Lu, {Liang Ying} and Lin, {Bo Chi} and Su, {Alan P.}",

year = "2012",

month = dec,

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doi = "10.1109/APCCAS.2012.6419051",

language = "English",

isbn = "9781457717291",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "380--383",

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note = "2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 ; Conference date: 02-12-2012 Through 05-12-2012",

}

Chiou, L-Y, Lu, LY, Lin, BC & Su, AP 2012, Buffer size minimization method considering mix-clock domains and discontinuous data access. in 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012., 6419051, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 380-383, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, 12-12-02. https://doi.org/10.1109/APCCAS.2012.6419051

Buffer size minimization method considering mix-clock domains and discontinuous data access. / Chiou, Lih-Yih; Lu, Liang Ying; Lin, Bo Chi; Su, Alan P.

2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. 2012. p. 380-383 6419051 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.

AB - We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.

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Buffer size minimization method considering mix-clock domains and discontinuous data access

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