TY - GEN
T1 - Buffer size minimization method considering mix-clock domains and discontinuous data access
AU - Chiou, Lih-Yih
AU - Lu, Liang Ying
AU - Lin, Bo Chi
AU - Su, Alan P.
PY - 2012/12/1
Y1 - 2012/12/1
N2 - We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.
AB - We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.
UR - http://www.scopus.com/inward/record.url?scp=84874139096&partnerID=8YFLogxK
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U2 - 10.1109/APCCAS.2012.6419051
DO - 10.1109/APCCAS.2012.6419051
M3 - Conference contribution
AN - SCOPUS:84874139096
SN - 9781457717291
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 380
EP - 383
BT - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
T2 - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Y2 - 2 December 2012 through 5 December 2012
ER -