Built-in intermediate voltage testing for CMOS circuits

Jing Jou Tang, Kuen Jong Lee, Bin Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

In this paper, we propose 4 new testing technique called built-in intermediate voltage testing for CMOS circuits. This technique provides 4 high quality test which cannot be achieved by conventional functional testing. Three novel circuit designs that can detect faults resulting in intermediate voltage values are presented. These designs can also be used to detect slow transition faults and the metastability of flip-Pops. The detection speed, area overhead, circuit complezity, and the performance impact on the circuits under test are analyzed. The results validate the feasibility of these designs in CMOS testing.

Original languageEnglish
Title of host publicationProceedings of the 1995 European Conference on Design and Test, EDTC 1995
PublisherAssociation for Computing Machinery, Inc
Pages372-376
Number of pages5
ISBN (Electronic)0818670398, 9780818670398
DOIs
Publication statusPublished - 1995 Mar 6
Event1995 European Conference on Design and Test, EDTC 1995 - Paris, France
Duration: 1995 Mar 61995 Mar 9

Publication series

NameProceedings of the 1995 European Conference on Design and Test, EDTC 1995

Other

Other1995 European Conference on Design and Test, EDTC 1995
Country/TerritoryFrance
CityParis
Period95-03-0695-03-09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

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