Built-In Redundancy Analysis for Memory Yield Improvement

Chih Tsun Huang, Chi Feng Wu, Jin Fu Li, Cheng Wen Wu

Research output: Contribution to journalArticle

149 Citations (Scopus)


With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.

Original languageEnglish
Pages (from-to)386-399
Number of pages14
JournalIEEE Transactions on Reliability
Issue number4
Publication statusPublished - 2003 Dec 1

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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