Abstract
Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.
| Original language | English |
|---|---|
| Pages (from-to) | 45-50 |
| Number of pages | 6 |
| Journal | Proceedings of the Asian Test Symposium |
| Publication status | Published - 2000 Dec 1 |
| Event | 9th Asian Test Symposium - Taipei, Taiwan Duration: 2000 Dec 4 → 2000 Dec 6 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Built-in self-test and self-diagnosis scheme for embedded SRAM. / Wang, Chih Wea; Wu, Chi Feng; Li, Jin Fu; Wu, Cheng Wen; Teng, Tony; Chiu, Kevin; Lin, Hsiao Ping.
In: Proceedings of the Asian Test Symposium, 01.12.2000, p. 45-50.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Built-in self-test and self-diagnosis scheme for embedded SRAM
AU - Wang, Chih Wea
AU - Wu, Chi Feng
AU - Li, Jin Fu
AU - Wu, Cheng Wen
AU - Teng, Tony
AU - Chiu, Kevin
AU - Lin, Hsiao Ping
PY - 2000/12/1
Y1 - 2000/12/1
N2 - Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.
AB - Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.
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M3 - Conference article
AN - SCOPUS:0034496878
SP - 45
EP - 50
JO - Proceedings of the Asian Test Symposium
JF - Proceedings of the Asian Test Symposium
SN - 1081-7735
ER -