Built-in self-test and self-diagnosis scheme for embedded SRAM

Chih Wea Wang, Chi Feng Wu, Jin Fu Li, Cheng Wen Wu, Tony Teng, Kevin Chiu, Hsiao Ping Lin

Research output: Contribution to journalConference article

35 Citations (Scopus)

Abstract

Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.

Original languageEnglish
Pages (from-to)45-50
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 2000 Dec 1
Event9th Asian Test Symposium - Taipei, Taiwan
Duration: 2000 Dec 42000 Dec 6

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Built-in self test
Static random access storage
Data storage equipment
Failure analysis
Hardware
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Wang, C. W., Wu, C. F., Li, J. F., Wu, C. W., Teng, T., Chiu, K., & Lin, H. P. (2000). Built-in self-test and self-diagnosis scheme for embedded SRAM. Proceedings of the Asian Test Symposium, 45-50.
Wang, Chih Wea ; Wu, Chi Feng ; Li, Jin Fu ; Wu, Cheng Wen ; Teng, Tony ; Chiu, Kevin ; Lin, Hsiao Ping. / Built-in self-test and self-diagnosis scheme for embedded SRAM. In: Proceedings of the Asian Test Symposium. 2000 ; pp. 45-50.
@article{c6c171aba9114d148adb879611db4124,
title = "Built-in self-test and self-diagnosis scheme for embedded SRAM",
abstract = "Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4{\%} for a typical 128 Kb SRAM and only 0.65{\%} for a 2 Mb SRAM.",
author = "Wang, {Chih Wea} and Wu, {Chi Feng} and Li, {Jin Fu} and Wu, {Cheng Wen} and Tony Teng and Kevin Chiu and Lin, {Hsiao Ping}",
year = "2000",
month = "12",
day = "1",
language = "English",
pages = "45--50",
journal = "Proceedings of the Asian Test Symposium",
issn = "1081-7735",
publisher = "IEEE Computer Society",

}

Wang, CW, Wu, CF, Li, JF, Wu, CW, Teng, T, Chiu, K & Lin, HP 2000, 'Built-in self-test and self-diagnosis scheme for embedded SRAM', Proceedings of the Asian Test Symposium, pp. 45-50.

Built-in self-test and self-diagnosis scheme for embedded SRAM. / Wang, Chih Wea; Wu, Chi Feng; Li, Jin Fu; Wu, Cheng Wen; Teng, Tony; Chiu, Kevin; Lin, Hsiao Ping.

In: Proceedings of the Asian Test Symposium, 01.12.2000, p. 45-50.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Built-in self-test and self-diagnosis scheme for embedded SRAM

AU - Wang, Chih Wea

AU - Wu, Chi Feng

AU - Li, Jin Fu

AU - Wu, Cheng Wen

AU - Teng, Tony

AU - Chiu, Kevin

AU - Lin, Hsiao Ping

PY - 2000/12/1

Y1 - 2000/12/1

N2 - Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.

AB - Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.

UR - http://www.scopus.com/inward/record.url?scp=0034496878&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034496878&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034496878

SP - 45

EP - 50

JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

SN - 1081-7735

ER -