TY - JOUR
T1 - Built-In Test and Diagnosis for TSVs with Different Placement Topologies and Crosstalk Impact Ranges
AU - Hsu, Wen Hsuan
AU - Kochte, Michael Andreas
AU - Lee, Kuen Jong
N1 - Funding Information:
This work was supported by the Ministry of Science and Technology of Taiwan under Grant 102-2221-E-006-270-MY3 and Grant 104-2811-E-006-036. This paper was recommended by Associate Editor H.-G. Stratigopoulos.
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2017/6
Y1 - 2017/6
N2 - Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design. This paper addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges, and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as many TSVs as possible are tested simultaneously. Based on the results of the TSV grouping, we implement a high-efficiency, low-area-overhead TSV test architecture that reuses the existing boundary scan or IEEE 1500 wrapper cells typically present for prebond testing. Experimental results show the short test and diagnosis time as well as the low area overhead of the proposed test architecture.
AB - Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design. This paper addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges, and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as many TSVs as possible are tested simultaneously. Based on the results of the TSV grouping, we implement a high-efficiency, low-area-overhead TSV test architecture that reuses the existing boundary scan or IEEE 1500 wrapper cells typically present for prebond testing. Experimental results show the short test and diagnosis time as well as the low area overhead of the proposed test architecture.
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U2 - 10.1109/TCAD.2016.2613928
DO - 10.1109/TCAD.2016.2613928
M3 - Article
AN - SCOPUS:85027530689
SN - 0278-0070
VL - 36
SP - 1004
EP - 1017
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 6
ER -