TY - GEN
T1 - Cache Write Generate for high performance parallel processing
AU - Wittenbrink, C. M.
AU - Somani, A. K.
AU - Chen, C. H.
PY - 1992
Y1 - 1992
N2 - Summary form only given. Generate, a new cache write handling scheme that avoids unnecessary reads from main memory, reduces bus contention, and increases the available bandwidth of the memory, is presented. Cache Write Generate increases the amount of CPU execution and memory load/store overlap, and decreases the memory cycle time. The performance of cache write generate is compared with that of write around and write allocate in single processor and shared bus multiprocessors and demonstrate a speedup of 1.2 to 1.5 over allocate and write around.
AB - Summary form only given. Generate, a new cache write handling scheme that avoids unnecessary reads from main memory, reduces bus contention, and increases the available bandwidth of the memory, is presented. Cache Write Generate increases the amount of CPU execution and memory load/store overlap, and decreases the memory cycle time. The performance of cache write generate is compared with that of write around and write allocate in single processor and shared bus multiprocessors and demonstrate a speedup of 1.2 to 1.5 over allocate and write around.
UR - http://www.scopus.com/inward/record.url?scp=0026868991&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0026868991&partnerID=8YFLogxK
U2 - 10.1145/139669.140899
DO - 10.1145/139669.140899
M3 - Conference contribution
AN - SCOPUS:0026868991
SN - 0897915097
SN - 9780897915090
T3 - Conference Proceedings - Annual Symposium on Computer Architecture
BT - Conference Proceedings - Annual Symposium on Computer Architecture
PB - Publ by IEEE
T2 - 19th International Symposium on Computer Architecture
Y2 - 19 May 1992 through 21 May 1992
ER -