Cache Write Generate for high performance parallel processing

C. M. Wittenbrink, A. K. Somani, C. H. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Summary form only given. Generate, a new cache write handling scheme that avoids unnecessary reads from main memory, reduces bus contention, and increases the available bandwidth of the memory, is presented. Cache Write Generate increases the amount of CPU execution and memory load/store overlap, and decreases the memory cycle time. The performance of cache write generate is compared with that of write around and write allocate in single processor and shared bus multiprocessors and demonstrate a speedup of 1.2 to 1.5 over allocate and write around.

Original languageEnglish
Title of host publicationConference Proceedings - Annual Symposium on Computer Architecture
PublisherPubl by IEEE
Number of pages1
ISBN (Print)0897915097, 9780897915090
DOIs
Publication statusPublished - 1992
Event19th International Symposium on Computer Architecture - Gold Coast, Aust
Duration: 1992 May 191992 May 21

Publication series

NameConference Proceedings - Annual Symposium on Computer Architecture

Other

Other19th International Symposium on Computer Architecture
CityGold Coast, Aust
Period92-05-1992-05-21

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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