Cache write generate for high performance parallel processing

C. M. Wittenbrink, A. K. Somani, Chung-Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present, Generate, a new cache write handling scheme that avoids unnecessary reads from main memory, reduces bus contention, and increases the available bandwidth of the memory. Cache Write Generate increases the amount of CPU execution and memory load/store overlap, and decreases the memory cycle time. We compare the performance of cache write generate with write around and write allocate in single processor and shared bus multiprocessors and demonstrate a speedup of 1.2 to 1.5 over allocate and write around.

Original languageEnglish
Title of host publicationProceedings of the Ninth Annual International Symposium on Computer Architecture
PublisherPubl by ACM
Number of pages1
ISBN (Print)0897915097
Publication statusPublished - 1993 Dec 1
EventProceedings of the 19th Annual International Symposium on Compu- ter Architecture - Gold Coast, Aust
Duration: 1992 May 191992 May 21

Publication series

NameProceedings of the Ninth Annual International Symposium on Computer Architecture

Other

OtherProceedings of the 19th Annual International Symposium on Compu- ter Architecture
CityGold Coast, Aust
Period92-05-1992-05-21

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Wittenbrink, C. M., Somani, A. K., & Chen, C-H. (1993). Cache write generate for high performance parallel processing. In Proceedings of the Ninth Annual International Symposium on Computer Architecture (Proceedings of the Ninth Annual International Symposium on Computer Architecture). Publ by ACM.