TY - GEN
T1 - Cache write generate for high performance parallel processing
AU - Wittenbrink, C. M.
AU - Somani, A. K.
AU - Chen, Chung-Ho
PY - 1993/12/1
Y1 - 1993/12/1
N2 - We present, Generate, a new cache write handling scheme that avoids unnecessary reads from main memory, reduces bus contention, and increases the available bandwidth of the memory. Cache Write Generate increases the amount of CPU execution and memory load/store overlap, and decreases the memory cycle time. We compare the performance of cache write generate with write around and write allocate in single processor and shared bus multiprocessors and demonstrate a speedup of 1.2 to 1.5 over allocate and write around.
AB - We present, Generate, a new cache write handling scheme that avoids unnecessary reads from main memory, reduces bus contention, and increases the available bandwidth of the memory. Cache Write Generate increases the amount of CPU execution and memory load/store overlap, and decreases the memory cycle time. We compare the performance of cache write generate with write around and write allocate in single processor and shared bus multiprocessors and demonstrate a speedup of 1.2 to 1.5 over allocate and write around.
UR - http://www.scopus.com/inward/record.url?scp=0027872108&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0027872108&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027872108
SN - 0897915097
T3 - Proceedings of the Ninth Annual International Symposium on Computer Architecture
BT - Proceedings of the Ninth Annual International Symposium on Computer Architecture
PB - Publ by ACM
T2 - Proceedings of the 19th Annual International Symposium on Compu- ter Architecture
Y2 - 19 May 1992 through 21 May 1992
ER -