Cache write generate for parallel image processing on shared memory architectures

Craig M. Wittenbrink; Arun K. Somani; Chung Ho Chen

doi:10.1109/83.502410

Cache write generate for parallel image processing on shared memory architectures

Craig M. Wittenbrink, Arun K. Somani, Chung Ho Chen

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

Original language	English
Pages (from-to)	1204-1208
Number of pages	5
Journal	IEEE Transactions on Image Processing
Volume	5
Issue number	7
DOIs	https://doi.org/10.1109/83.502410
Publication status	Published - 1996

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design

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abstract = "We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.",

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