Cache write generate for parallel image processing on shared memory architectures

Craig M. Wittenbrink; Arun K. Somani; Chung Ho Chen

doi:10.1109/83.502410

Cache write generate for parallel image processing on shared memory architectures

Craig M. Wittenbrink, Arun K. Somani, Chung Ho Chen

Institute of Computer and Communication Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

Original language	English
Pages (from-to)	1204-1208
Number of pages	5
Journal	IEEE Transactions on Image Processing
Volume	5
Issue number	7
DOIs	https://doi.org/10.1109/83.502410
Publication status	Published - 1996

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design

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10.1109/83.502410

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@article{c70514b14e194a6197697c94150c4e9f,

title = "Cache write generate for parallel image processing on shared memory architectures",

abstract = "We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.",

author = "Wittenbrink, {Craig M.} and Somani, {Arun K.} and Chen, {Chung Ho}",

year = "1996",

doi = "10.1109/83.502410",

language = "English",

volume = "5",

pages = "1204--1208",

journal = "IEEE Transactions on Image Processing",

issn = "1057-7149",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - Cache write generate for parallel image processing on shared memory architectures

AU - Wittenbrink, Craig M.

AU - Somani, Arun K.

AU - Chen, Chung Ho

PY - 1996

Y1 - 1996

N2 - We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

AB - We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

UR - http://www.scopus.com/inward/record.url?scp=0030193898&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030193898&partnerID=8YFLogxK

U2 - 10.1109/83.502410

DO - 10.1109/83.502410

M3 - Article

C2 - 18285208

AN - SCOPUS:0030193898

VL - 5

SP - 1204

EP - 1208

JO - IEEE Transactions on Image Processing

JF - IEEE Transactions on Image Processing

SN - 1057-7149

IS - 7

ER -

Cache write generate for parallel image processing on shared memory architectures

Abstract

All Science Journal Classification (ASJC) codes

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