TY - JOUR
T1 - Cache write generate for parallel image processing on shared memory architectures
AU - Wittenbrink, Craig M.
AU - Somani, Arun K.
AU - Chen, Chung Ho
N1 - Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.
PY - 1996
Y1 - 1996
N2 - We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.
AB - We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.
UR - http://www.scopus.com/inward/record.url?scp=0030193898&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030193898&partnerID=8YFLogxK
U2 - 10.1109/83.502410
DO - 10.1109/83.502410
M3 - Article
C2 - 18285208
AN - SCOPUS:0030193898
VL - 5
SP - 1204
EP - 1208
JO - IEEE Transactions on Image Processing
JF - IEEE Transactions on Image Processing
SN - 1057-7149
IS - 7
ER -