A capacitor-less low-power low-dropout regulator (LDR) with a slew-rate-enhanced circuit (SRE) was proposed. The SRE uses six transistors to constitute two comparators and two auxiliary transistors. The comparators sense the variation of load current to control one of the auxiliary transistors that generate a large current to charge or discharge the gate capacitor of the power transistor; thus SRE increases the slew-rate at the gate of the power transistor. The quiescent current of the LDR remains 18 μA at the steady state because the auxiliary transistors work at the cut-off region to reduce power consumption. When load current changes between 0.1 and 100 mA, the variation of the output voltage of the LDR is improved from 675 to 300 mV.
All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
- Electrical and Electronic Engineering