Capture-power-safe test pattern determination for at-speed scan-based testing

Yi Hua Li, Wei Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76% on average with little or no fault coverage loss.

Original languageEnglish
Article number6685941
Pages (from-to)127-138
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume33
Issue number1
DOIs
Publication statusPublished - 2014 Jan 1

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Testing
Refining
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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abstract = "During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75{\%} of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76{\%} on average with little or no fault coverage loss.",
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Capture-power-safe test pattern determination for at-speed scan-based testing. / Li, Yi Hua; Lien, Wei Cheng; Lin, Ing-Chao; Lee, Kuen-Jong.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 1, 6685941, 01.01.2014, p. 127-138.

Research output: Contribution to journalArticle

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