Cell delay fault testing for iterative logic arrays

Shyue Kung Lu, Cheng Wen Wu, Ruei Zong Hwang

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)


C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.

Original languageEnglish
Pages (from-to)311-316
Number of pages6
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Issue number3
Publication statusPublished - 1996 Jan 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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