Characterization of fine-pitch solder bump joint and package warpage for low K high-pin-count flip-chip BGA through Shadow Moiré and Micro Moiré techniques

An Hong Liu, David W. Wang, Hsiang Ming Huang, Ming Sun, Muh Ren Lin, Chonghua Zhong, Sheng Jye Hwang, Hsuan Heng Lu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Flip chip-substrate interconnect joint reliability using either leaded, lead-free solder bumps or more recent Cu pillar, has been well recognized since the first flip chip package was developed and started volume production. Recently the relative displacement between the bump and bump pad, induced by package warpage, has received significantly increasing interest, especially for those devices with low K dielectric and fine-pitch interconnects (solder bump, eutectic tin-lead, lead free or Cu pillar), as the pitch becomes smaller and the package body size becomes larger. In order to quantitatively characterize the physical relation between package micron-level warpage and solder bump nano-level displacement, a systematic study of warpage characteristics of 1112-ball flip-chip BGA with and without a heat spreader was carried out in this study, using both Shadow Moiré technique and Micro Moiré interferometry. Shadow Moiré technique was used to characterize the overall package warpage between room temperature and solder ball reflow temperature of 230 C. Micro Moiré interferometry was carried out at temperature range from room temperature to 114C. Effects of a heat spreader on the total package warpage were characterized through Shadow Moiré measurement which clearly showed it is effective to alter the warpage pattern of a package from convex(w/o) to concave(w/), while the package warpage of both types of packages were well-controlled under 16um. Furthermore, the correlation between Shadow Moiré and Micro Moiré is also described in this study. A close correlation between two interferometry results is established. This study develops a very useful physical method enables a direct and quantitative estimation of solder bump displacement in terms of package-level warpage. Results can be used to evaluate chip-level interconnect reliability, packaging design and materials selection, particularly, for the next generation of Si nodes and the implementation of new low-K dielectric.

Original languageEnglish
Title of host publication2011 IEEE 61st Electronic Components and Technology Conference, ECTC 2011
Pages431-440
Number of pages10
DOIs
Publication statusPublished - 2011 Jul 21
Event2011 61st Electronic Components and Technology Conference, ECTC 2011 - Lake Buena Vista, FL, United States
Duration: 2011 May 312011 Jun 3

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Other

Other2011 61st Electronic Components and Technology Conference, ECTC 2011
CountryUnited States
CityLake Buena Vista, FL
Period11-05-3111-06-03

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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