Chip implementation of a 1.5-GHz gain-control phase shifter

Hung Chi Wang, Chi Yuan Lu, Jyh Ching Juang, Chun Lin Lu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 1.5-GHz RF gain-control phase-shifter fabricated in TSMC 0.18-μm CMOS process. The vector-synthesis topology is applied in this work to achieve a wide range phase-shift from 0° -360° for the processed RF signal. A gain-control buffer amplifier is added immediately after the phase-synthesizer to compensate the signal attenuation. The measured maximum attenuation is -21 dB for each of four attenuators which are the core circuits of the phase-synthesizer. The measured gain-control range of the buffer amplifier is around -16 dB at 1.5 GHz. The power consumption of the chip is 14.4mW under 1.8 V power supply. The chip size is 0.74 × 0.68 mm 2.

Original languageEnglish
Title of host publication3rd International Conference on Innovative Computing Information and Control, ICICIC'08
DOIs
Publication statusPublished - 2008
Event3rd International Conference on Innovative Computing Information and Control, ICICIC'08 - Dalian, Liaoning, China
Duration: 2008 Jun 182008 Jun 20

Publication series

Name3rd International Conference on Innovative Computing Information and Control, ICICIC'08

Other

Other3rd International Conference on Innovative Computing Information and Control, ICICIC'08
Country/TerritoryChina
CityDalian, Liaoning
Period08-06-1808-06-20

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Software
  • Control and Systems Engineering

Fingerprint

Dive into the research topics of 'Chip implementation of a 1.5-GHz gain-control phase shifter'. Together they form a unique fingerprint.

Cite this