CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm21.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA

Ting Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Embedded FPGAs (eFPGA) are increasingly being used in SoCs, enabling post-silicon hardware specialization. Existing CPU-eFPGA SoCs have three deficiencies. First, their low core count hinders efficient execution of thread-level-parallel workloads. Second, noncoherent or partially coherent CPU-eFPGA integration inhibits dynamic, random memory sharing. Third, the use of full-custom circuits makes proprietary eFPGAs technology-dependent, inflexible in physical layout, and lacking architectural customizability.

Original languageEnglish
Title of host publication2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350399486
DOIs
Publication statusPublished - 2023
Event44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023 - San Antonio, United States
Duration: 2023 Apr 232023 Apr 26

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2023-April
ISSN (Print)0886-5930

Conference

Conference44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023
Country/TerritoryUnited States
CitySan Antonio
Period23-04-2323-04-26

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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