CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm21.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA

Ting Jung Chang; Ang Li; Fei Gao; Tuan Ta; Georgios Tziantzioulis; Yanghui Ou; Moyang Wang; Jinzheng Tu; Kaifeng Xu; Paul J. Jackson; August Ning; Grigory Chirkov; Marcelo Orenes-Vera; Shady Agwa; Xiaoyu Yan; Eric Tang; Jonathan Balkind; Christopher Batten; David Wentzlaff

doi:10.1109/CICC57935.2023.10121294

CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm²1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA

Ting Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

MS Degree in Intelligent Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Embedded FPGAs (eFPGA) are increasingly being used in SoCs, enabling post-silicon hardware specialization. Existing CPU-eFPGA SoCs have three deficiencies. First, their low core count hinders efficient execution of thread-level-parallel workloads. Second, noncoherent or partially coherent CPU-eFPGA integration inhibits dynamic, random memory sharing. Third, the use of full-custom circuits makes proprietary eFPGAs technology-dependent, inflexible in physical layout, and lacking architectural customizability.

Original language	English
Title of host publication	2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350399486
DOIs	https://doi.org/10.1109/CICC57935.2023.10121294
Publication status	Published - 2023
Event	44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023 - San Antonio, United States Duration: 2023 Apr 23 → 2023 Apr 26

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2023-April
ISSN (Print)	0886-5930

Conference

Conference	44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023
Country/Territory	United States
City	San Antonio
Period	23-04-23 → 23-04-26

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/CICC57935.2023.10121294

Cite this

Chang, T. J., Li, A., Gao, F., Ta, T., Tziantzioulis, G., Ou, Y., Wang, M., Tu, J., Xu, K., Jackson, P. J., Ning, A., Chirkov, G., Orenes-Vera, M., Agwa, S., Yan, X., Tang, E., Balkind, J., Batten, C., & Wentzlaff, D. (2023). CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm²1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. In 2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings (Proceedings of the Custom Integrated Circuits Conference; Vol. 2023-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC57935.2023.10121294

@inproceedings{54436eb1b0f14480b4aa873590542575,

title = "CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm21.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA",

abstract = "Embedded FPGAs (eFPGA) are increasingly being used in SoCs, enabling post-silicon hardware specialization. Existing CPU-eFPGA SoCs have three deficiencies. First, their low core count hinders efficient execution of thread-level-parallel workloads. Second, noncoherent or partially coherent CPU-eFPGA integration inhibits dynamic, random memory sharing. Third, the use of full-custom circuits makes proprietary eFPGAs technology-dependent, inflexible in physical layout, and lacking architectural customizability.",

author = "Chang, {Ting Jung} and Ang Li and Fei Gao and Tuan Ta and Georgios Tziantzioulis and Yanghui Ou and Moyang Wang and Jinzheng Tu and Kaifeng Xu and Jackson, {Paul J.} and August Ning and Grigory Chirkov and Marcelo Orenes-Vera and Shady Agwa and Xiaoyu Yan and Eric Tang and Jonathan Balkind and Christopher Batten and David Wentzlaff",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023 ; Conference date: 23-04-2023 Through 26-04-2023",

year = "2023",

doi = "10.1109/CICC57935.2023.10121294",

language = "English",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings",

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Chang, TJ, Li, A, Gao, F, Ta, T, Tziantzioulis, G, Ou, Y, Wang, M, Tu, J, Xu, K, Jackson, PJ, Ning, A, Chirkov, G, Orenes-Vera, M, Agwa, S, Yan, X, Tang, E, Balkind, J, Batten, C & Wentzlaff, D 2023, CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm²1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. in 2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings. Proceedings of the Custom Integrated Circuits Conference, vol. 2023-April, Institute of Electrical and Electronics Engineers Inc., 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, United States, 23-04-23. https://doi.org/10.1109/CICC57935.2023.10121294

CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm²1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. / Chang, Ting Jung; Li, Ang; Gao, Fei et al.
2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings of the Custom Integrated Circuits Conference; Vol. 2023-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Chang, Ting Jung

AU - Li, Ang

AU - Gao, Fei

AU - Ta, Tuan

AU - Tziantzioulis, Georgios

AU - Ou, Yanghui

AU - Wang, Moyang

AU - Tu, Jinzheng

AU - Xu, Kaifeng

AU - Jackson, Paul J.

AU - Ning, August

AU - Chirkov, Grigory

AU - Orenes-Vera, Marcelo

AU - Agwa, Shady

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AU - Wentzlaff, David

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AB - Embedded FPGAs (eFPGA) are increasingly being used in SoCs, enabling post-silicon hardware specialization. Existing CPU-eFPGA SoCs have three deficiencies. First, their low core count hinders efficient execution of thread-level-parallel workloads. Second, noncoherent or partially coherent CPU-eFPGA integration inhibits dynamic, random memory sharing. Third, the use of full-custom circuits makes proprietary eFPGAs technology-dependent, inflexible in physical layout, and lacking architectural customizability.

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T3 - Proceedings of the Custom Integrated Circuits Conference

BT - 2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 23 April 2023 through 26 April 2023

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Chang TJ, Li A, Gao F, Ta T, Tziantzioulis G, Ou Y et al. CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm²1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. In 2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC57935.2023.10121294