Combinational circuit fault diagnosis using logic emulation

Shyue Kung Lu; Jian Long Chen; Cheng Wen Wu; Wen Feng Chang; Shi Yu Huang

Combinational circuit fault diagnosis using logic emulation

Shyue Kung Lu, Jian Long Chen, Cheng Wen Wu, Wen Feng Chang, Shi Yu Huang

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

5 Citations (Scopus)

Abstract

We propose an emulation-based diagnosis technique for combinational circuits in this paper. To verify our approach, a hardware emulator is implemented by using Altera MAX+Plus II CPLD Development System. Our approach reduces the CPU time required by a software-based diagnosis technique significantly, and greatly eliminates the hardware requirements with circuit partitioning techniques and novel fault injection elements (FIEs). Moreover, our diagnosis algorithm also decreases the times of simulation when performing diagnosis. Experimental results for ISCAS-85 benchmark circuits show that our emulation system is 45 times faster than Kokan's [1] on the average.

Original language	English
Pages (from-to)	V549-V552
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
Publication status	Published - 2003 Jul 14
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 2003 May 25 → 2003 May 28

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "Combinational circuit fault diagnosis using logic emulation",

abstract = "We propose an emulation-based diagnosis technique for combinational circuits in this paper. To verify our approach, a hardware emulator is implemented by using Altera MAX+Plus II CPLD Development System. Our approach reduces the CPU time required by a software-based diagnosis technique significantly, and greatly eliminates the hardware requirements with circuit partitioning techniques and novel fault injection elements (FIEs). Moreover, our diagnosis algorithm also decreases the times of simulation when performing diagnosis. Experimental results for ISCAS-85 benchmark circuits show that our emulation system is 45 times faster than Kokan's [1] on the average.",

author = "Lu, {Shyue Kung} and Chen, {Jian Long} and Wu, {Cheng Wen} and Chang, {Wen Feng} and Huang, {Shi Yu}",

year = "2003",

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note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

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TY - JOUR

T1 - Combinational circuit fault diagnosis using logic emulation

AU - Lu, Shyue Kung

AU - Chen, Jian Long

AU - Wu, Cheng Wen

AU - Chang, Wen Feng

AU - Huang, Shi Yu

PY - 2003/7/14

Y1 - 2003/7/14

N2 - We propose an emulation-based diagnosis technique for combinational circuits in this paper. To verify our approach, a hardware emulator is implemented by using Altera MAX+Plus II CPLD Development System. Our approach reduces the CPU time required by a software-based diagnosis technique significantly, and greatly eliminates the hardware requirements with circuit partitioning techniques and novel fault injection elements (FIEs). Moreover, our diagnosis algorithm also decreases the times of simulation when performing diagnosis. Experimental results for ISCAS-85 benchmark circuits show that our emulation system is 45 times faster than Kokan's [1] on the average.

AB - We propose an emulation-based diagnosis technique for combinational circuits in this paper. To verify our approach, a hardware emulator is implemented by using Altera MAX+Plus II CPLD Development System. Our approach reduces the CPU time required by a software-based diagnosis technique significantly, and greatly eliminates the hardware requirements with circuit partitioning techniques and novel fault injection elements (FIEs). Moreover, our diagnosis algorithm also decreases the times of simulation when performing diagnosis. Experimental results for ISCAS-85 benchmark circuits show that our emulation system is 45 times faster than Kokan's [1] on the average.

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M3 - Conference article

AN - SCOPUS:0037743886

VL - 5

SP - V549-V552

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

Combinational circuit fault diagnosis using logic emulation

Abstract

All Science Journal Classification (ASJC) codes

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