Combinational circuit fault diagnosis using logic emulation

Shyue Kung Lu, Jian Long Chen, Cheng Wen Wu, Wen Feng Chang, Shi Yu Huang

Research output: Contribution to journalConference articlepeer-review

5 Citations (Scopus)


We propose an emulation-based diagnosis technique for combinational circuits in this paper. To verify our approach, a hardware emulator is implemented by using Altera MAX+Plus II CPLD Development System. Our approach reduces the CPU time required by a software-based diagnosis technique significantly, and greatly eliminates the hardware requirements with circuit partitioning techniques and novel fault injection elements (FIEs). Moreover, our diagnosis algorithm also decreases the times of simulation when performing diagnosis. Experimental results for ISCAS-85 benchmark circuits show that our emulation system is 45 times faster than Kokan's [1] on the average.

Original languageEnglish
Pages (from-to)V549-V552
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2003 Jul 14
EventProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 2003 May 252003 May 28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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