Combinatorial methodologies applied to the advanced CMOS gate stack

K. S. Chang, N. D. Bassim, P. K. Schenck, J. Suehle, I. Takeuchi, M. L. Green

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As the CMOS gate stack continues to scale to smaller dimensions, new materials must be introduced into the stack to keep pace with design requirements. One way to measure the properties of new materials systems is through the use of high-throughput experimentation, called combinatorial methodology. We describe two examples of combinatorial experimental design for CMOS. In the first, we will demonstrate library design and growth of Al-Hf-Y-O films for high-k applications. In the second, we will demonstrate Ni-Ti-Pt metal gate libraries for Si/Hf02/metal gate electrode applications.

Original languageEnglish
Title of host publicationCHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS
Subtitle of host publication2007 International Conference on Frontiers of Characterization and Metrology
Pages297-302
Number of pages6
DOIs
Publication statusPublished - 2007
EventCHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology - Gaithersburg, MD, United States
Duration: 2007 Mar 272007 Mar 29

Publication series

NameAIP Conference Proceedings
Volume931
ISSN (Print)0094-243X
ISSN (Electronic)1551-7616

Other

OtherCHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology
CountryUnited States
CityGaithersburg, MD
Period07-03-2707-03-29

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy(all)

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