Combinatorial methodologies applied to the advanced CMOS gate stack

Kao-Shuo Chang, N. D. Bassim, P. K. Schenck, J. Suehle, I. Takeuchi, M. L. Green

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As the CMOS gate stack continues to scale to smaller dimensions, new materials must be introduced into the stack to keep pace with design requirements. One way to measure the properties of new materials systems is through the use of high-throughput experimentation, called combinatorial methodology. We describe two examples of combinatorial experimental design for CMOS. In the first, we will demonstrate library design and growth of Al-Hf-Y-O films for high-k applications. In the second, we will demonstrate Ni-Ti-Pt metal gate libraries for Si/Hf02/metal gate electrode applications.

Original languageEnglish
Title of host publicationCHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS
Subtitle of host publication2007 International Conference on Frontiers of Characterization and Metrology
Pages297-302
Number of pages6
DOIs
Publication statusPublished - 2007 Oct 22
EventCHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology - Gaithersburg, MD, United States
Duration: 2007 Mar 272007 Mar 29

Publication series

NameAIP Conference Proceedings
Volume931
ISSN (Print)0094-243X
ISSN (Electronic)1551-7616

Other

OtherCHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology
CountryUnited States
CityGaithersburg, MD
Period07-03-2707-03-29

Fingerprint

CMOS
methodology
experimentation
metals
requirements
electrodes

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy(all)

Cite this

Chang, K-S., Bassim, N. D., Schenck, P. K., Suehle, J., Takeuchi, I., & Green, M. L. (2007). Combinatorial methodologies applied to the advanced CMOS gate stack. In CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology (pp. 297-302). (AIP Conference Proceedings; Vol. 931). https://doi.org/10.1063/1.2799387
Chang, Kao-Shuo ; Bassim, N. D. ; Schenck, P. K. ; Suehle, J. ; Takeuchi, I. ; Green, M. L. / Combinatorial methodologies applied to the advanced CMOS gate stack. CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology. 2007. pp. 297-302 (AIP Conference Proceedings).
@inproceedings{5bf2edfd101848a8aac9b67fad5643b6,
title = "Combinatorial methodologies applied to the advanced CMOS gate stack",
abstract = "As the CMOS gate stack continues to scale to smaller dimensions, new materials must be introduced into the stack to keep pace with design requirements. One way to measure the properties of new materials systems is through the use of high-throughput experimentation, called combinatorial methodology. We describe two examples of combinatorial experimental design for CMOS. In the first, we will demonstrate library design and growth of Al-Hf-Y-O films for high-k applications. In the second, we will demonstrate Ni-Ti-Pt metal gate libraries for Si/Hf02/metal gate electrode applications.",
author = "Kao-Shuo Chang and Bassim, {N. D.} and Schenck, {P. K.} and J. Suehle and I. Takeuchi and Green, {M. L.}",
year = "2007",
month = "10",
day = "22",
doi = "10.1063/1.2799387",
language = "English",
isbn = "0735404410",
series = "AIP Conference Proceedings",
pages = "297--302",
booktitle = "CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS",

}

Chang, K-S, Bassim, ND, Schenck, PK, Suehle, J, Takeuchi, I & Green, ML 2007, Combinatorial methodologies applied to the advanced CMOS gate stack. in CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology. AIP Conference Proceedings, vol. 931, pp. 297-302, CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology, Gaithersburg, MD, United States, 07-03-27. https://doi.org/10.1063/1.2799387

Combinatorial methodologies applied to the advanced CMOS gate stack. / Chang, Kao-Shuo; Bassim, N. D.; Schenck, P. K.; Suehle, J.; Takeuchi, I.; Green, M. L.

CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology. 2007. p. 297-302 (AIP Conference Proceedings; Vol. 931).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Combinatorial methodologies applied to the advanced CMOS gate stack

AU - Chang, Kao-Shuo

AU - Bassim, N. D.

AU - Schenck, P. K.

AU - Suehle, J.

AU - Takeuchi, I.

AU - Green, M. L.

PY - 2007/10/22

Y1 - 2007/10/22

N2 - As the CMOS gate stack continues to scale to smaller dimensions, new materials must be introduced into the stack to keep pace with design requirements. One way to measure the properties of new materials systems is through the use of high-throughput experimentation, called combinatorial methodology. We describe two examples of combinatorial experimental design for CMOS. In the first, we will demonstrate library design and growth of Al-Hf-Y-O films for high-k applications. In the second, we will demonstrate Ni-Ti-Pt metal gate libraries for Si/Hf02/metal gate electrode applications.

AB - As the CMOS gate stack continues to scale to smaller dimensions, new materials must be introduced into the stack to keep pace with design requirements. One way to measure the properties of new materials systems is through the use of high-throughput experimentation, called combinatorial methodology. We describe two examples of combinatorial experimental design for CMOS. In the first, we will demonstrate library design and growth of Al-Hf-Y-O films for high-k applications. In the second, we will demonstrate Ni-Ti-Pt metal gate libraries for Si/Hf02/metal gate electrode applications.

UR - http://www.scopus.com/inward/record.url?scp=35348834110&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=35348834110&partnerID=8YFLogxK

U2 - 10.1063/1.2799387

DO - 10.1063/1.2799387

M3 - Conference contribution

SN - 0735404410

SN - 9780735404410

T3 - AIP Conference Proceedings

SP - 297

EP - 302

BT - CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS

ER -

Chang K-S, Bassim ND, Schenck PK, Suehle J, Takeuchi I, Green ML. Combinatorial methodologies applied to the advanced CMOS gate stack. In CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology. 2007. p. 297-302. (AIP Conference Proceedings). https://doi.org/10.1063/1.2799387