Combined 2-D transform and quantization architectures for H.264 video coders

Heng Yao Lin; Yi Chih Chao; Che Hong Chen; Bin Da Liu; Jar Ferr Yang

doi:10.1109/ISCAS.2005.1464959

Combined 2-D transform and quantization architectures for H.264 video coders

Heng Yao Lin, Yi Chih Chao, Che Hong Chen, Bin Da Liu, Jar Ferr Yang

Research output: Contribution to journal › Conference article › peer-review

42 Citations (Scopus)

Abstract

In this paper, the low-complexity hardware architectures of 4×4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into transform step, which results in the reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 μm technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in encoder part and 448 M samples/sec at 56 MHz in decoder part, respectively.

Original language	English
Article number	1464959
Pages (from-to)	1802-1805
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464959
Publication status	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 2005 May 23 → 2005 May 26

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ISCAS.2005.1464959

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title = "Combined 2-D transform and quantization architectures for H.264 video coders",

abstract = "In this paper, the low-complexity hardware architectures of 4×4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into transform step, which results in the reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 μm technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in encoder part and 448 M samples/sec at 56 MHz in decoder part, respectively.",

author = "Lin, {Heng Yao} and Chao, {Yi Chih} and Chen, {Che Hong} and Liu, {Bin Da} and Yang, {Jar Ferr}",

year = "2005",

doi = "10.1109/ISCAS.2005.1464959",

language = "English",

pages = "1802--1805",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

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TY - JOUR

T1 - Combined 2-D transform and quantization architectures for H.264 video coders

AU - Lin, Heng Yao

AU - Chao, Yi Chih

AU - Chen, Che Hong

AU - Liu, Bin Da

AU - Yang, Jar Ferr

PY - 2005

Y1 - 2005

N2 - In this paper, the low-complexity hardware architectures of 4×4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into transform step, which results in the reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 μm technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in encoder part and 448 M samples/sec at 56 MHz in decoder part, respectively.

AB - In this paper, the low-complexity hardware architectures of 4×4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into transform step, which results in the reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 μm technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in encoder part and 448 M samples/sec at 56 MHz in decoder part, respectively.

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M3 - Conference article

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SP - 1802

EP - 1805

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1464959

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

Combined 2-D transform and quantization architectures for H.264 video coders

Abstract

All Science Journal Classification (ASJC) codes

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