Combined CAVLC decoder and inverse quantizer for efficient H.264/AVC decoding

Yi Chih Chao, Shih Tse Wei, Jar-Ferr Yang, Bin-Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, we propose an efficient architecture, which combines the context-based adaptive variable length coding (CAVLC) decoder and inverse quantization (IQ) together to simplify the H.264/AVC decoder. The IQ function is effectively moved to the run_before stage in the CAVLC decoder. With this efficient arrangement, we can easily implement the interface between CAVLC decoder and IQ without additional logic circuit. However, we also use pipeline skill to improve the performance. Because there are data dependency properties in the CAVLC decoder, we should modify the algorithm in the standard to realize the pipeline skill. We implement this architecture with UMC 0.18 μm cell library. The simulation results show the operation frequency can achieve 200 MHz. The total number of logic gate counts is 9.23k. For the real-time requirement, it achieves 1080HD (1920×1088) @30 frames/sec while the clock frequency is set to 195 MHz.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages259-262
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 2006 Dec 42006 Dec 6

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
CountrySingapore
Period06-12-0406-12-06

Fingerprint

Decoding
Pipelines
Logic gates
Logic circuits
Clocks

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Chao, Y. C., Wei, S. T., Yang, J-F., & Liu, B-D. (2006). Combined CAVLC decoder and inverse quantizer for efficient H.264/AVC decoding. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 259-262). [4145380] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342381
Chao, Yi Chih ; Wei, Shih Tse ; Yang, Jar-Ferr ; Liu, Bin-Da. / Combined CAVLC decoder and inverse quantizer for efficient H.264/AVC decoding. APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. pp. 259-262 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).
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Chao, YC, Wei, ST, Yang, J-F & Liu, B-D 2006, Combined CAVLC decoder and inverse quantizer for efficient H.264/AVC decoding. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145380, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 259-262, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06-12-04. https://doi.org/10.1109/APCCAS.2006.342381

Combined CAVLC decoder and inverse quantizer for efficient H.264/AVC decoding. / Chao, Yi Chih; Wei, Shih Tse; Yang, Jar-Ferr; Liu, Bin-Da.

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 259-262 4145380 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chao YC, Wei ST, Yang J-F, Liu B-D. Combined CAVLC decoder and inverse quantizer for efficient H.264/AVC decoding. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 259-262. 4145380. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342381