TY - JOUR
T1 - Combined CAVLC decoder, inverse quantizer, and transform kernel in compact H.264/AVC decoder
AU - Chao, Yi Chih
AU - Wei, Shih Tse
AU - Liu, Bin Da
AU - Yang, Jar Ferr
N1 - Funding Information:
Manuscript received November 16, 2007; revised March 25, 2008. First published December 09, 2008; current version published January 21, 2009. This work was supported in part by the National Science Council of Taiwan under Grant NSC 96-2220-E-006-002. This paper was recommended by Associate Editor H. Sun.
Copyright:
Copyright 2009 Elsevier B.V., All rights reserved.
PY - 2009/1
Y1 - 2009/1
N2 - In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4 × 4 inverse integer transform, the 4 × 4 inverse Hadamard transform and the 2 × 2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format.
AB - In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4 × 4 inverse integer transform, the 4 × 4 inverse Hadamard transform and the 2 × 2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format.
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U2 - 10.1109/TCSVT.2008.2009251
DO - 10.1109/TCSVT.2008.2009251
M3 - Article
AN - SCOPUS:58449129474
SN - 1051-8215
VL - 19
SP - 53
EP - 62
JO - IEEE Transactions on Circuits and Systems for Video Technology
JF - IEEE Transactions on Circuits and Systems for Video Technology
IS - 1
M1 - 4703220
ER -