Combined CAVLC decoder, inverse quantizer, and transform kernel in compact H.264/AVC decoder

Yi Chih Chao, Shih Tse Wei, Bin Da Liu, Jar Ferr Yang

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4 × 4 inverse integer transform, the 4 × 4 inverse Hadamard transform and the 2 × 2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format.

Original languageEnglish
Article number4703220
Pages (from-to)53-62
Number of pages10
JournalIEEE Transactions on Circuits and Systems for Video Technology
Issue number1
Publication statusPublished - 2009 Jan

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Electrical and Electronic Engineering


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