Compact modeling for new transistor structures

C. Hu, M. Dunga, C. H. Lin, Darsen Lu, A. Niknejad

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

Using embedded SRAM as a path, FinFET may enter manufacturing at 32nm. FinFET provides several advantages over the planar MOSFET structure-smaller size, larger current, smaller leakage, and less variation in threshold voltage. A compact model of multi-gate transistors will facilitate their adoption. BSIM-MG is a surface-potential based compact model of multi-gate MOSFETs fabricated on either SOI or bulk substrates. The effects of body doping are modeled. It can also model a double-gate transistor with independently biased front and back gates and asymmetric front and back gate work-functions and dielectric thicknesses.

Original languageEnglish
Pages285-288
Number of pages4
Publication statusPublished - 2007 Jan 1
Event12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 - Vienna, Austria
Duration: 2007 Sep 252007 Sep 27

Other

Other12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
CountryAustria
CityVienna
Period07-09-2507-09-27

Fingerprint

Transistors
MOSFET
Modeling
Surface Potential
Static random access storage
Surface potential
Threshold voltage
Leakage
Biased
Manufacturing
Voltage
Substrate
Doping (additives)
Model
Path
Substrates
FinFET

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Modelling and Simulation

Cite this

Hu, C., Dunga, M., Lin, C. H., Lu, D., & Niknejad, A. (2007). Compact modeling for new transistor structures. 285-288. Paper presented at 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.
Hu, C. ; Dunga, M. ; Lin, C. H. ; Lu, Darsen ; Niknejad, A. / Compact modeling for new transistor structures. Paper presented at 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.4 p.
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Hu, C, Dunga, M, Lin, CH, Lu, D & Niknejad, A 2007, 'Compact modeling for new transistor structures' Paper presented at 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria, 07-09-25 - 07-09-27, pp. 285-288.

Compact modeling for new transistor structures. / Hu, C.; Dunga, M.; Lin, C. H.; Lu, Darsen; Niknejad, A.

2007. 285-288 Paper presented at 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.

Research output: Contribution to conferencePaper

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Hu C, Dunga M, Lin CH, Lu D, Niknejad A. Compact modeling for new transistor structures. 2007. Paper presented at 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.