Compact modeling for new transistor structures

C. Hu, M. Dunga, C. H. Lin, D. Lu, A. Niknejad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Using embedded SRAM as a path, FinFET may enter manufacturing at 32nm. FinFET provides several advantages over the planar MOSFET structure-smaller size, larger current, smaller leakage, and less variation in threshold voltage. A compact model of multi-gate transistors will facilitate their adoption. BSIM-MG is a surface-potential based compact model of multi-gate MOSFETs fabricated on either SOI or bulk substrates. The effects of body doping are modeled. It can also model a double-gate transistor with independently biased front and back gates and asymmetric front and back gate work-functions and dielectric thicknesses.

Original languageEnglish
Title of host publication2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
PublisherSpringer-Verlag Wien
Pages285-288
Number of pages4
ISBN (Print)9783211728604
DOIs
Publication statusPublished - 2007
Event12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 - Vienna, Austria
Duration: 2007 Sep 252007 Sep 27

Publication series

Name2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

Other

Other12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
CountryAustria
CityVienna
Period07-09-2507-09-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Modelling and Simulation

Fingerprint Dive into the research topics of 'Compact modeling for new transistor structures'. Together they form a unique fingerprint.

Cite this