TY - JOUR
T1 - Comparative studies of normally-off Al0.26Ga0.74N/AlN/GaN/Si high electron mobility transistors with different gate structures
AU - Lee, Ching Sung
AU - Hsu, Wei Chou
AU - Liu, Han Yin
AU - Chen, Si Fu
AU - Chen, Yu Chang
AU - Yang, Shen Tin
N1 - Publisher Copyright:
© 2017 Elsevier Ltd
PY - 2017/8/1
Y1 - 2017/8/1
N2 - Systematic designs to achieve normally-off operation and improved device performance for Al0.26Ga0.74N/AlN/GaN high electron mobility transistors (HEMTs) grown on a Si substrate are investigated in this work. The step-by-step approach includes: (1) devising a thin AlGaN/AlN composite barrier, (2) introducing fluoride ions within the active region by using CF4 plasma treatment, (3) growing the Al2O3 oxide passivation layers within gate-drain/source regions by using a cost-effective ozone water oxidization technique, and (4) integrating a metal-oxide-semiconductor gate (MOS-gate) design with high-k Al2O3 gate dielectric. Devices with four different evolutionary gate structures have been compared and studied. Variations of threshold voltage (Vth), Hooge coefficients (αH), maximum drain-source current density (IDS, max), maximum extrinsic transconductance (gm, max), gate-voltage swing (GVS) linearity, two-terminal gate-drain breakdown/turn-on voltages (BVGD/Von), on/off current ratio (Ion/Ioff), and high-temperature characteristics up to 450 K are also investigated.
AB - Systematic designs to achieve normally-off operation and improved device performance for Al0.26Ga0.74N/AlN/GaN high electron mobility transistors (HEMTs) grown on a Si substrate are investigated in this work. The step-by-step approach includes: (1) devising a thin AlGaN/AlN composite barrier, (2) introducing fluoride ions within the active region by using CF4 plasma treatment, (3) growing the Al2O3 oxide passivation layers within gate-drain/source regions by using a cost-effective ozone water oxidization technique, and (4) integrating a metal-oxide-semiconductor gate (MOS-gate) design with high-k Al2O3 gate dielectric. Devices with four different evolutionary gate structures have been compared and studied. Variations of threshold voltage (Vth), Hooge coefficients (αH), maximum drain-source current density (IDS, max), maximum extrinsic transconductance (gm, max), gate-voltage swing (GVS) linearity, two-terminal gate-drain breakdown/turn-on voltages (BVGD/Von), on/off current ratio (Ion/Ioff), and high-temperature characteristics up to 450 K are also investigated.
UR - http://www.scopus.com/inward/record.url?scp=85017091351&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85017091351&partnerID=8YFLogxK
U2 - 10.1016/j.mssp.2017.03.034
DO - 10.1016/j.mssp.2017.03.034
M3 - Article
AN - SCOPUS:85017091351
SN - 1369-8001
VL - 66
SP - 39
EP - 43
JO - Materials Science in Semiconductor Processing
JF - Materials Science in Semiconductor Processing
ER -