Complimentary single-electron/hole action of nanoscale SOI CMOS transistors

Yaohui Zhang, Filipp A. Baron, Kang L. Wang, Zoran Krivokapic

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

We propose a new device structure for room-temperature single-electron/hole transistors based on nanosize narrow-width fully depleted silicon-on-insulator (SOI) CMOS transistors. The floating body of SOI MOSFETs can become a Coulomb island, whose single charging energy is more than 30 meV, as the gate length and width of MOSFETs is less than 10 nm. As SOI MOSFETs are biased at accumulation, single-electron, or hole tunnels, are sent, one by one, from the source to the floating body and then to the drain via Zener tunneling process. N-channel SOI MOSFETs can have the functions of single-electron transistors (n-SETs) while p-channel MOSFETs can have the functions of single-hole transistors (p-SETs). SOI MOSFETs still behave as typical MOSFETs when biased at inversion. There is a gate voltage margin of 0.9 V to separate Coulomb blockade oscillations from CMOS normal operation.

Original languageEnglish
Pages (from-to)492-494
Number of pages3
JournalIEEE Electron Device Letters
Volume25
Issue number7
DOIs
Publication statusPublished - 2004 Jul

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Complimentary single-electron/hole action of nanoscale SOI CMOS transistors'. Together they form a unique fingerprint.

Cite this