Concentrator circuit with multiple priority levels

A. V. Krishnamoorthy; Lih Yih Chiou; R. G. Rozier; O. Kibar

doi:10.1049/el:20000287

Concentrator circuit with multiple priority levels

A. V. Krishnamoorthy, Lih Yih Chiou, R. G. Rozier, O. Kibar

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology.

Original language	English
Pages (from-to)	500-501
Number of pages	2
Journal	Electronics Letters
Volume	36
Issue number	6
DOIs	https://doi.org/10.1049/el:20000287
Publication status	Published - 2000 Mar 16

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:20000287

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@article{76e85b2552fe42d6ba953c8741a2b761,

title = "Concentrator circuit with multiple priority levels",

abstract = "The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology.",

author = "Krishnamoorthy, {A. V.} and Chiou, {Lih Yih} and Rozier, {R. G.} and O. Kibar",

year = "2000",

month = mar,

day = "16",

doi = "10.1049/el:20000287",

language = "English",

volume = "36",

pages = "500--501",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "6",

}

TY - JOUR

T1 - Concentrator circuit with multiple priority levels

AU - Krishnamoorthy, A. V.

AU - Chiou, Lih Yih

AU - Rozier, R. G.

AU - Kibar, O.

PY - 2000/3/16

Y1 - 2000/3/16

N2 - The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology.

AB - The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=0033877243&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033877243&partnerID=8YFLogxK

U2 - 10.1049/el:20000287

DO - 10.1049/el:20000287

M3 - Article

AN - SCOPUS:0033877243

VL - 36

SP - 500

EP - 501

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 6

ER -