Abstract
The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology.
Original language | English |
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Pages (from-to) | 500-501 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 36 |
Issue number | 6 |
DOIs | |
Publication status | Published - 2000 Mar 16 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering