Concentrator circuit with multiple priority levels

A. V. Krishnamoorthy, Lih Yih Chiou, R. G. Rozier, O. Kibar

Research output: Contribution to journalArticlepeer-review


The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology.

Original languageEnglish
Pages (from-to)500-501
Number of pages2
JournalElectronics Letters
Issue number6
Publication statusPublished - 2000 Mar 16

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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