Conditional capacitor averaging technique to reduce nonlinearity induced by capacitor mismatch in 2.5-bit/stage pipelined ADCs

Tz Jing Shau, Jin Fu Lin, Soon Jyh Chang, Chih Hao Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a conditional capacitor averaging technique to enhance the linearity of 2.5-bit/stage high-resolution pipelined ADCs with capacitor mismatch. Design concepts of capacitor averaging and sorting techniques are employed to mitigate the error effect of capacitor mismatch. Moreover, the sorted capacitors and digital-to-digital converter (DAC) voltages in a 2.5-bit multiplying analog-to-digital converter (MDAC) are well configured to further enhance the linearity of the pipelined ADC. Only slight circuit modification of an MDAC and minor additional digital circuits are required for a pipelined ADC with the proposed technique. Simulation results demonstrate that dynamic and static performances of a 14-bit 2.5-bit/stage pipelined ADCs are improved significantly compared with previous techniques.

Original languageEnglish
Title of host publication2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages139-142
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
Duration: 2010 Nov 182010 Nov 19

Publication series

Name2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
CountryTaiwan
CityKaohsiung
Period10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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