This paper presents a conditional capacitor averaging technique to enhance the linearity of 2.5-bit/stage high-resolution pipelined ADCs with capacitor mismatch. Design concepts of capacitor averaging and sorting techniques are employed to mitigate the error effect of capacitor mismatch. Moreover, the sorted capacitors and digital-to-digital converter (DAC) voltages in a 2.5-bit multiplying analog-to-digital converter (MDAC) are well configured to further enhance the linearity of the pipelined ADC. Only slight circuit modification of an MDAC and minor additional digital circuits are required for a pipelined ADC with the proposed technique. Simulation results demonstrate that dynamic and static performances of a 14-bit 2.5-bit/stage pipelined ADCs are improved significantly compared with previous techniques.