Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Bing Yang Lin, Wan Ting Chiang, Cheng Wen Wu, Mincent Lee, Hung Chih Lin, Ching Nen Peng, Min Jer Wang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.

Original languageEnglish
Article number7154435
Pages (from-to)30-39
Number of pages10
JournalIEEE Design and Test
Volume33
Issue number2
DOIs
Publication statusPublished - 2016 Apr 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N., & Wang, M. J. (2016). Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Design and Test, 33(2), 30-39. [7154435]. https://doi.org/10.1109/MDAT.2015.2455347