Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Bing Yang Lin; Wan Ting Chiang; Cheng Wen Wu; Mincent Lee; Hung Chih Lin; Ching Nen Peng; Min Jer Wang

doi:10.1109/MDAT.2015.2455347

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Bing Yang Lin, Wan Ting Chiang, Cheng Wen Wu, Mincent Lee, Hung Chih Lin, Ching Nen Peng, Min Jer Wang

Department of Electrical Engineering

Research output: Contribution to journal › Article

1 Citation (Scopus)

Abstract

Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.

Original language	English
Article number	7154435
Pages (from-to)	30-39
Number of pages	10
Journal	IEEE Design and Test
Volume	33
Issue number	2
DOIs	https://doi.org/10.1109/MDAT.2015.2455347
Publication status	Published - 2016 Apr 1

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N., & Wang, M. J. (2016). Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Design and Test, 33(2), 30-39. [7154435]. https://doi.org/10.1109/MDAT.2015.2455347

@article{b6f4833eea054b20994674cd82bdde89,

title = "Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement",

abstract = "Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.",

author = "Lin, {Bing Yang} and Chiang, {Wan Ting} and Wu, {Cheng Wen} and Mincent Lee and Lin, {Hung Chih} and Peng, {Ching Nen} and Wang, {Min Jer}",

year = "2016",

month = apr,

day = "1",

doi = "10.1109/MDAT.2015.2455347",

language = "English",

volume = "33",

pages = "30--39",

journal = "IEEE Design and Test",

issn = "2168-2356",

publisher = "IEEE Computer Society",

number = "2",

}

TY - JOUR

T1 - Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

AU - Lin, Bing Yang

AU - Chiang, Wan Ting

AU - Wu, Cheng Wen

AU - Lee, Mincent

AU - Lin, Hung Chih

AU - Peng, Ching Nen

AU - Wang, Min Jer

PY - 2016/4/1

Y1 - 2016/4/1

N2 - Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.

AB - Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.

UR - http://www.scopus.com/inward/record.url?scp=84963934389&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84963934389&partnerID=8YFLogxK

U2 - 10.1109/MDAT.2015.2455347

DO - 10.1109/MDAT.2015.2455347

M3 - Article

AN - SCOPUS:84963934389

VL - 33

SP - 30

EP - 39

JO - IEEE Design and Test

JF - IEEE Design and Test

SN - 2168-2356

IS - 2

M1 - 7154435

ER -