Abstract
Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.
Original language | English |
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Article number | 7154435 |
Pages (from-to) | 30-39 |
Number of pages | 10 |
Journal | IEEE Design and Test |
Volume | 33 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2016 Apr 1 |
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering