Constraints for using IDDQ testing to detect CMOS bridging faults

Kuen-Jong Lee, M. A. Breuer

Research output: Contribution to conferencePaper

11 Citations (Scopus)

Abstract

Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.

Original languageEnglish
Pages303-308
Number of pages6
DOIs
Publication statusPublished - 1991 Jan 1
Event1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991 - Atlantic City, United States
Duration: 1991 Apr 151991 Apr 17

Conference

Conference1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991
CountryUnited States
CityAtlantic City
Period91-04-1591-04-17

Fingerprint

Networks (circuits)
Monitoring
Testing
Sequential circuits
Logic circuits

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Lee, K-J., & Breuer, M. A. (1991). Constraints for using IDDQ testing to detect CMOS bridging faults. 303-308. Paper presented at 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States. https://doi.org/10.1109/VTEST.1991.208175
Lee, Kuen-Jong ; Breuer, M. A. / Constraints for using IDDQ testing to detect CMOS bridging faults. Paper presented at 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States.6 p.
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Lee, K-J & Breuer, MA 1991, 'Constraints for using IDDQ testing to detect CMOS bridging faults', Paper presented at 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States, 91-04-15 - 91-04-17 pp. 303-308. https://doi.org/10.1109/VTEST.1991.208175

Constraints for using IDDQ testing to detect CMOS bridging faults. / Lee, Kuen-Jong; Breuer, M. A.

1991. 303-308 Paper presented at 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States.

Research output: Contribution to conferencePaper

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Lee K-J, Breuer MA. Constraints for using IDDQ testing to detect CMOS bridging faults. 1991. Paper presented at 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States. https://doi.org/10.1109/VTEST.1991.208175