Constraints for using IDDQ testing to detect CMOS bridging faults

Kuen Jong Lee; M. A. Breuer

doi:10.1109/VTEST.1991.208175

Constraints for using IDDQ testing to detect CMOS bridging faults

Kuen Jong Lee
, M. A. Breuer

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

12 Citations (Scopus)

Abstract

Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.

Original language	English
Pages	303-308
Number of pages	6
DOIs	https://doi.org/10.1109/VTEST.1991.208175
Publication status	Published - 1991
Event	1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991 - Atlantic City, United States Duration: 1991 Apr 15 → 1991 Apr 17

Conference

Conference	1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991
Country/Territory	United States
City	Atlantic City
Period	91-04-15 → 91-04-17

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

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10.1109/VTEST.1991.208175

Cite this

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abstract = "Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.",

author = "Lee, \{Kuen Jong\} and Breuer, \{M. A.\}",

note = "Funding Information: This work was supported by the Defense Advanced Research Projects Agency and monitored by the Office of Naval Research under Contract No. N00014-87-K-0861. The views and conclusions contained in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U. S. Government.; 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991 ; Conference date: 15-04-1991 Through 17-04-1991",

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doi = "10.1109/VTEST.1991.208175",

language = "English",

pages = "303--308",

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AU - Breuer, M. A.

N1 - Funding Information: This work was supported by the Defense Advanced Research Projects Agency and monitored by the Office of Naval Research under Contract No. N00014-87-K-0861. The views and conclusions contained in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U. S. Government.

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Y1 - 1991

N2 - Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.

AB - Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.

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Y2 - 15 April 1991 through 17 April 1991

ER -

Constraints for using IDDQ testing to detect CMOS bridging faults

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