Controlled misfit dislocation technology in strained silicon MOSFETs

San Lein Wu; Yen Ping Wang; Shoou Jinn Chang

doi:10.1088/0268-1242/21/1/008

Controlled misfit dislocation technology in strained silicon MOSFETs

San Lein Wu, Yen Ping Wang, Shoou Jinn Chang

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

In this paper, we report new process integration flows to fabricate strained-Si nMOSFETs having thicker strained-Si grown on a relaxed Si _0.8Ge_0.2 virtual substrate. For the same device parameters and process condition, a device with this advanced integration flow (sample B) starting epitaxial strained-Si layers after shallow trench isolation and well implantation is shown having a 70% enhancement in effective electron mobility compared to the Si control device. Devices with conventional process sequences (sample A) exhibit a larger leakage current and up to 50% device failure. The leakage mechanism in sample A due to misfit dislocation-induced leakage paths is clearly demonstrated from the photon emission microscopy (PEM) measurement. Improved characteristics in sample B indicate that devices with new process sequences exhibit controlled misfit dislocations in strained-Si layers and show a greater flexibility for developing high-performance strained-Si CMOS.

Original language	English
Pages (from-to)	44-47
Number of pages	4
Journal	Semiconductor Science and Technology
Volume	21
Issue number	1
DOIs	https://doi.org/10.1088/0268-1242/21/1/008
Publication status	Published - 2006 Jan 1

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1088/0268-1242/21/1/008

Cite this

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abstract = "In this paper, we report new process integration flows to fabricate strained-Si nMOSFETs having thicker strained-Si grown on a relaxed Si 0.8Ge0.2 virtual substrate. For the same device parameters and process condition, a device with this advanced integration flow (sample B) starting epitaxial strained-Si layers after shallow trench isolation and well implantation is shown having a 70% enhancement in effective electron mobility compared to the Si control device. Devices with conventional process sequences (sample A) exhibit a larger leakage current and up to 50% device failure. The leakage mechanism in sample A due to misfit dislocation-induced leakage paths is clearly demonstrated from the photon emission microscopy (PEM) measurement. Improved characteristics in sample B indicate that devices with new process sequences exhibit controlled misfit dislocations in strained-Si layers and show a greater flexibility for developing high-performance strained-Si CMOS.",

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AU - Wang, Yen Ping

AU - Chang, Shoou Jinn

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N2 - In this paper, we report new process integration flows to fabricate strained-Si nMOSFETs having thicker strained-Si grown on a relaxed Si 0.8Ge0.2 virtual substrate. For the same device parameters and process condition, a device with this advanced integration flow (sample B) starting epitaxial strained-Si layers after shallow trench isolation and well implantation is shown having a 70% enhancement in effective electron mobility compared to the Si control device. Devices with conventional process sequences (sample A) exhibit a larger leakage current and up to 50% device failure. The leakage mechanism in sample A due to misfit dislocation-induced leakage paths is clearly demonstrated from the photon emission microscopy (PEM) measurement. Improved characteristics in sample B indicate that devices with new process sequences exhibit controlled misfit dislocations in strained-Si layers and show a greater flexibility for developing high-performance strained-Si CMOS.

AB - In this paper, we report new process integration flows to fabricate strained-Si nMOSFETs having thicker strained-Si grown on a relaxed Si 0.8Ge0.2 virtual substrate. For the same device parameters and process condition, a device with this advanced integration flow (sample B) starting epitaxial strained-Si layers after shallow trench isolation and well implantation is shown having a 70% enhancement in effective electron mobility compared to the Si control device. Devices with conventional process sequences (sample A) exhibit a larger leakage current and up to 50% device failure. The leakage mechanism in sample A due to misfit dislocation-induced leakage paths is clearly demonstrated from the photon emission microscopy (PEM) measurement. Improved characteristics in sample B indicate that devices with new process sequences exhibit controlled misfit dislocations in strained-Si layers and show a greater flexibility for developing high-performance strained-Si CMOS.

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Controlled misfit dislocation technology in strained silicon MOSFETs

Abstract

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