Controller architecture for low-power, low-latency DRAM with built-in cache

Zhi Yong Liu, Hsiu Chuan Shih, Bing Yang Lin, Cheng Wen Wu

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


Memory wall is a critical issue for many today's electronic systems. Tiered latency DRAM with asymmetric bit lines was proposed to optimize the power and latency. This paper proposes a controller architecture for the tiered latency DRAM in which the small array is operated like a cache. - Jin-Fu Li, National Central University

Original languageEnglish
Article number7397924
Pages (from-to)69-78
Number of pages10
JournalIEEE Design and Test
Issue number2
Publication statusPublished - 2017 Apr 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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